Mellanox Technologies | Date: 2016-10-09
A host connected to at least one data network has a processor having a plurality of cores, and a memory. A network interface controller is coupled to the host, and configured to transmit and receive data packets via multiple distinct physical ports. The host and the network interface controller are cooperative upon receiving a packet for storing the packet in a receive buffer of the memory, deciding in the host, responsively to a destination identifier in the packet, to forward the packet from the host to the at least one data network via another one of the physical ports, and selecting one of the cores to perform a send operation.
Mellanox Technologies | Date: 2016-10-19
The invention comprises a multilevel optical signal system comprising two or more light source branches and an optical power-combiner, wherein each branch comprising a light source, an optical modulator and an electrical driver for the modulator, wherein each electrical driver is configured for being driven by electrical signals to drive the modulator to modulate the light generated by the light source into a corresponding 2-level data signalsuch that the respective 2-level data signals differs in power level.
Mellanox Technologies | Date: 2017-01-10
An inductive device is formed in a circuit structure that includes alternating conductive and insulating layers. The device includes, in a plurality of the conductive layers, traces forming a respective pair of interleaved loops and at least one interconnect segment in each of the plurality of the conductive layers. In each layer among the plurality of the conductive layers, at least one loop in the respective pair is closed by jumpers to an interconnect segment formed in another layer above or below the layer.
Mellanox Technologies | Date: 2017-03-28
Communication apparatus includes an input circuit, which receives a sequence of symbols arranged in a series of data blocks, including data symbols that encode the data and forward error correction (FEC) symbols that encode an error correction code. The input circuit decodes the data encoded by the data symbols and passes the decoded data to a buffer for output to a data link layer interface irrespective of the FEC symbols. An error correction circuit receives the data and the error correction code from the input circuit, and upon detecting an error in a given data block in the series, passes the corrected data from the given data block to the buffer for output to the data link layer interface in place of the data from the given data block that the input circuit decoded and passed to the buffer.
Mellanox Technologies | Date: 2017-03-28
A switching device includes a plurality of ports and a switching core, which is coupled to transfer data packets between ingress and egress ports. Switching logic maintains a descriptor queue containing respective descriptors corresponding to the data packets that have been received and queued by the ports, and responsively to the respective descriptors, instructs the switching core to transfer the queued data packets between the ports. Port logic, which is associated with each port, is configured, upon receipt of a data packet from the network at the port, to signal the switching logic to place a descriptor corresponding to the data packet in the descriptor queue and, upon identifying the data packet as meeting a predefined criterion, to convey a request to the switching logic, bypassing the descriptor queue, to instruct the switching core to transfer the data packet immediately to an egress port.
Agency: European Commission | Branch: H2020 | Program: RIA | Phase: ICT-06-2014 | Award Amount: 3.05M | Year: 2015
Datacentre traffic is experiencing 2-digit growth challenging the scalability of current network architectures. The new concept of disaggregation exacerbates bandwidth and latency demands whereas emerging cloud business opportunities urge for reliable inter-datacenter networking. PROJECT will develop an end-to-end solution extending from the datacenter architecture and optical subsystem design to the overlaying control plane and application interfaces. PROJECT hybrid electronic-optical network architecture scales linearly with the number of datacenter hosts, offers Ethernet granularity and saves up to 94% power and 30% cost. It consolidates compute and storage networks over a single, Ethernet optical TDMA network. Low latency, hardware-level dynamic re-configurability and quasi-deterministic QoS are supported in view of disaggregated datacenter deployment scenarios. A fully functional control plane overlay will be developed comprising an SDN controller along with its interfaces. The southbound interface abstracts physical layer infrastructure and allows dynamic hardware-level network reconfigurability. The northbound interface links the SDN controller with the application requirements through an Application Programming Interface. PROJECT innovative control plane enables Application Defined Networking and merges hardware and software virtualization over the hybrid optical infrastructure. It also integrates SDN modules and functions for inter-datacenter connectivity, enabling dynamic bandwidth allocation based on the needs of migrating VMs as well as on existing Service Level Agreements for transparent networking among telecom and datacenter operators domains. Fully-functional network subsystems will be prototyped: a 400Gb/s hybrid Top-of-Rack switch, a 50Gb/s electronic-optical smart Network Interface Card and a fast optical pod switch. PROJECT concept will be demonstrated in the lab and in its operational environment for both intra- and inter-datacenter scenario
Agency: European Commission | Branch: H2020 | Program: RIA | Phase: ICT-27-2015 | Award Amount: 4.15M | Year: 2016
PLASMOfab aims to address the ever increasing needs for low energy, small size, high complexity and high performance mass manufactured PICs by developing a revolutionary yet CMOS-compatible fabrication platform for seamless co-integration of active plasmonics with photonic and supporting electronic. The CMOS-compatible metals Aluminum, Titanium Nitride and Copper, will be thoroughly investigated towards establishing a pool of meaningful elementary plasmonic waveguides on co-planar photonic (Si, SiO2 and SiN) platforms along with the associated photonic-plasmonic interfaces. The functional advantages of PLASMOfab technology will be practically demonstrated by developing two novel functional prototypes with outstanding performances: 1) a compact, plasmonic bio-sensor for label-free inflammation markers detection with multichannel capabilities and record-high sensitivity by combining plasmonic sensors with electrical contacts, Si3N4 photonics, high-speed biofunctionalization techniques and microfluidics 2) a 100 Gb/s NRZ transmitter for datacom applications by consolidating low energy and low footprint plasmonic modulator and ultra high-speed SiGe driving electronics in a single monolithic chip. The new integration technology will be verified through wafer-scale fabrication of the prototypes at commercial CMOS fabs, demonstrating volume manufacturing and cost reduction capabilities. PLASMOfab technology will be supported by an EDA software design kit library paving the way for a standardized, fabless plasmonic/photonic IC eco-system.
Mellanox Technologies | Date: 2016-08-30
Optical apparatus connecting a Silicon Photonics (SiP) device, which comprises multiple optical waveguides to an array of collimating lenses, configured to collimate light of the multiple optical waveguides into collimated beams. The optical apparatus includes a deflection element, distinct from the SiP device, including a light deflection surface which deflects light from the waveguides by an angle greater than 30 degrees, to the array of collimating lenses.
Mellanox Technologies | Date: 2016-03-23
A method for communication includes receiving multiple work requests from a process running on a computer to transmit respective messages over a network. A single work item corresponding to the multiple work requests is submitted to a network interface controller (NIC) connected to the computer. In response to the single work item, multiple data packets carrying the respective messages are transmitted from the NIC to the network.
Mellanox Technologies | Date: 2016-06-09
A method for computing includes submitting a first command from a central processing unit (CPU) to a first peripheral device in a computer to write data in a first bus transaction over a peripheral component bus in the computer to a second peripheral device in the computer. A second command is submitted from the CPU to one of the first and second peripheral devices to execute a second bus transaction, subsequent to the first bus transaction, that will flush the data from the peripheral component bus to the second peripheral device. The first and second bus transactions are executed in response to the first and second commands. Following completion of the second bus transaction, the second peripheral device processes the written data in.