Mellanox Technologies | Date: 2017-03-28
Communication apparatus includes an input circuit, which receives a sequence of symbols arranged in a series of data blocks, including data symbols that encode the data and forward error correction (FEC) symbols that encode an error correction code. The input circuit decodes the data encoded by the data symbols and passes the decoded data to a buffer for output to a data link layer interface irrespective of the FEC symbols. An error correction circuit receives the data and the error correction code from the input circuit, and upon detecting an error in a given data block in the series, passes the corrected data from the given data block to the buffer for output to the data link layer interface in place of the data from the given data block that the input circuit decoded and passed to the buffer.
Mellanox Technologies | Date: 2017-03-28
A switching device includes a plurality of ports and a switching core, which is coupled to transfer data packets between ingress and egress ports. Switching logic maintains a descriptor queue containing respective descriptors corresponding to the data packets that have been received and queued by the ports, and responsively to the respective descriptors, instructs the switching core to transfer the queued data packets between the ports. Port logic, which is associated with each port, is configured, upon receipt of a data packet from the network at the port, to signal the switching logic to place a descriptor corresponding to the data packet in the descriptor queue and, upon identifying the data packet as meeting a predefined criterion, to convey a request to the switching logic, bypassing the descriptor queue, to instruct the switching core to transfer the data packet immediately to an egress port.
Mellanox Technologies | Date: 2017-09-06
A memory device includes a target memory, having a memory address space, and a volatile buffer memory, which is coupled to receive data written over a bus to the memory device for storage in specified addresses within the memory address space. A memory controller is configured to receive, via the bus, a flush instruction and, in response to the flush instruction, to immediately flush the data held in the buffer memory with specified addresses within the memory address space to the target memory.
Mellanox Technologies | Date: 2016-08-30
A switch in a data network is configured to mediate data exchanges among network elements. The apparatus further includes a processor, which organizes the network elements into a hierarchical tree having a root node network element, vertex node network elements child node network elements that include leaf node network elements. The leaf node network elements are originate aggregation data and transmit the aggregation data to respective parent vertex node network elements. The vertex node network elements combine the aggregation data from at least a portion of the child node network elements, and transmit the combined aggregation data from the vertex node network elements to parent vertex node network elements. The root node network element is operative for initiating a reduction operation on the aggregation data.
Mellanox Technologies | Date: 2016-08-02
Communication apparatus includes a plurality of interfaces configured to be connected to a Layer-3 packet network and to serve as ingress and egress interfaces to receive and transmit packets from and to the network. Routing logic is coupled to process respective Layer-3 headers of the packets received through the ingress interfaces and to route the packets via the egress interfaces to respective destinations indicated by the Layer-3 headers. Congestion detection logic is coupled to identify a flow of the received packets that is causing congestion in the network and a Layer-3 address from which the flow originates, and to direct the routing logic to route a backward congestion notification message (CNM) packet via one of the egress interfaces to the identified Layer-3 address.
Mellanox Technologies | Date: 2016-09-28
A method for congestion control includes receiving at a destination computer a packet transmitted on a given flow, in accordance with a predefined transport protocol, through a network by a transmitting network interface controller (NIC) of a source computer, and marked by an element in the network with a forward congestion notification. Upon receiving the marked packet in a receiving NIC of the destination computer, a congestion notification packet (CNP) indicating a flow to be throttled is immediately queued for transmission from the receiving NIC through the network to the source computer. Upon receiving the CNP in the transmitting NIC, transmission of further packets on at least the flow indicated by the CNP from the transmitting NIC to the network is immediately throttled, and an indication of the given flow is passed from the transmitting NIC to a protocol processing software stack running on the source computer.
Mellanox Technologies | Date: 2016-11-20
A method for communication, includes routing unicast data packets among nodes in a network using respective Layer-3 addresses that are uniquely assigned to each of the nodes. Respective Layer-2 unicast addresses are assigned to the nodes in accordance with an algorithmic mapping of the respective Layer-3 addresses. The unicast data packets are forwarded within subnets of the network using the assigned Layer-2 addresses.
Mellanox Technologies | Date: 2017-01-10
An inductive device is formed in a circuit structure that includes alternating conductive and insulating layers. The device includes, in a plurality of the conductive layers, traces forming a respective pair of interleaved loops and at least one interconnect segment in each of the plurality of the conductive layers. In each layer among the plurality of the conductive layers, at least one loop in the respective pair is closed by jumpers to an interconnect segment formed in another layer above or below the layer.
Mellanox Technologies | Date: 2017-09-13
In a fabric of network elements one network element has an object pool (60) to be accessed stored in its memory. A request for atomic access to the object pool (60) by another network element is carried out by transmitting the request through the fabric to the one network element, performing a remote direct memory access to a designated member of the object pool (60), atomically executing the request, and returning a result of the execution of the request through the fabric to the other network element.
Agency: European Commission | Branch: H2020 | Program: RIA | Phase: ICT-27-2015 | Award Amount: 4.15M | Year: 2016
PLASMOfab aims to address the ever increasing needs for low energy, small size, high complexity and high performance mass manufactured PICs by developing a revolutionary yet CMOS-compatible fabrication platform for seamless co-integration of active plasmonics with photonic and supporting electronic. The CMOS-compatible metals Aluminum, Titanium Nitride and Copper, will be thoroughly investigated towards establishing a pool of meaningful elementary plasmonic waveguides on co-planar photonic (Si, SiO2 and SiN) platforms along with the associated photonic-plasmonic interfaces. The functional advantages of PLASMOfab technology will be practically demonstrated by developing two novel functional prototypes with outstanding performances: 1) a compact, plasmonic bio-sensor for label-free inflammation markers detection with multichannel capabilities and record-high sensitivity by combining plasmonic sensors with electrical contacts, Si3N4 photonics, high-speed biofunctionalization techniques and microfluidics 2) a 100 Gb/s NRZ transmitter for datacom applications by consolidating low energy and low footprint plasmonic modulator and ultra high-speed SiGe driving electronics in a single monolithic chip. The new integration technology will be verified through wafer-scale fabrication of the prototypes at commercial CMOS fabs, demonstrating volume manufacturing and cost reduction capabilities. PLASMOfab technology will be supported by an EDA software design kit library paving the way for a standardized, fabless plasmonic/photonic IC eco-system.