MediaTek Inc.

Hsinchu, Taiwan

MediaTek Inc.

Hsinchu, Taiwan

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A semiconductor package includes a first substrate, a second substrate, a composite solder ball and a first semiconductor component. The composite solder ball includes a core, an encapsulating layer and a barrier layer. The composite solder ball is disposed between the first substrate and the second substrate for electrically connecting the first substrate and the second substrate. The barrier layer is disposed between the core and the encapsulating layer. Wherein a melting point of the barrier layer is higher than a melting point of the core, the melting point of the core is higher than a melting point of the encapsulating layer. The first semiconductor component is disposed between the first substrate and the second substrate.


Patent
MediaTek Inc. | Date: 2017-05-17

An amplifier system (100) includes a main amplifier (110), a cross-over current detector (120) and a controller (130). The main amplifier (110) includes at least a first driving transistor (MD1) and a second driving transistor (MD2) serving as a differential pair, wherein the first driving transistor (MD1) and the second driving transistor (MD2) are arranged to receive a first input signal and a second input signal, respectively. The cross-over current detector (120) is coupled to the main amplifier (110), and is arranged for detecting a cross-over current of the main amplifier (110), wherein the cross-over current of the main amplifier (110) is an overlapped current from the differential pair. The controller (130) is coupled to the main amplifier (110) and the cross-over current detector (120), and is arranged for generating a control signal to control a gain of the main amplifier (110) according to an output of the main amplifier (110) and the cross-over current of the main amplifier (110).


The present invention provides a control circuit (1 20) to stabilize an output power of a power amplifier (110). The control circuit (120) comprises a voltage clamping loop (1 30), a current clamping loop (140) and a loop (1 50) for reducing power variation under VSWR, where the voltage clamping loop (1 30) is used to clamp an output voltage of the power amplifier (110) within a defined voltage range, the current clamping loop (140) is used to clamp a current of the power amplifier (110) within a defined current range, and the loop (1 50) for reducing power variation under VSWR is implemented by an impedance detector (1 50) to compensate the output power under VSWR variation.


Patent
MediaTek Inc. | Date: 2017-05-17

The invention provides a semiconductor package assembly. The semiconductor package assembly includes a redistribution layer (RDL) structure having a first surface and a second surface opposite to the first substrate. The RDL structure includes a redistribution layer (RDL) contact pad arranged close to the second surface. A passivation layer is disposed on the RDL contact pad. The passivation layer has an opening corresponding to the RDL contact pad such that the RDL contact pad is exposed to the opening. A first distance between a first position of the opening and a central point of the opening is different from a second distance between a second position of the opening and the central point of the opening in a plan view.


Signaling methods to support robust interference cancellation by obtaining information associated with interfering signals from the network side are provided. The target interference for cancellation is intra-cell interference from Multi-User Multi-Input-Multi-Output (MU-MIMO) or Non-Orthogonal Multiple Access (NOMA) operation. A victim receiver receives both desired signal and intra-cell interfering signal. The network may assist the victim receiver by providing information related to the interfering signal. The computational complexity of the victim receiver in blindly detecting the interfering signal characteristics is reduced, and the reliability of the signal detection is improved.


Patent
MediaTek Inc. | Date: 2017-05-17

A method of direction finding (DF) positioning based on a simplified antenna platform format in a wireless communication network is proposed. A receiver receives antenna platform format information of a transmitter having multiple antenna elements. The antenna platform format information comprises an antenna platform format indicator, antenna platform position and orientation information, a number of antenna elements, and switching delay, phase center, and polarization information for each antenna element. The receiver receives a plurality of direction finding sounding signals transmitted from the transmitter via the multiple antenna elements. The receiver performs a DF algorithm based on the plurality of DF sounding signals and the antenna platform format information and thereby estimating a DF solution. Finally, the receiver determines its own location information based on the estimated DF solution.


A method for performing signal control of an electronic device and an associated apparatus are provided, where the method includes the steps of: when it is detected that a phase difference between a data signal and a clock signal reaches a predetermined value, controlling the clock signal to switch from a first frequency to a second frequency, wherein both of the clock signal and the data signal are signals of the electronic device (e.g. signals of a memory interface circuit of the electronic device); applying at least one phase shift to the data signal until a condition is satisfied; and controlling the clock signal to switch from the second frequency to the first frequency; wherein the data signal is calibrated with respect to the clock signal with aid of the at least one phase shift.


Patent
MediaTek Inc. | Date: 2017-05-24

The invention provides a semiconductor package assembly (500g, 500h). The semiconductor package assembly includes a first semiconductor package including a first redistribution layer (400) (RDL) structure having a first surface (401) and a second surface (403) opposite to the first substrate. The first RDL structure includes a plurality of first conductive traces (402) close to the first surface of the first RDL structure. An antenna pattern (404) is disposed close to the second surface of the first RDL structure. A first semiconductor die (410) is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. A plurality of conductive structures (226) is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. The plurality of conductive structures is spaced apart from the antenna pattern through the plurality of first conductive traces of the first RDL structure.


Methods are provided for concurrent communications among multiple wireless communications devices. In one novel aspect, the wireless station transmits a wideband signal to a plurality of wireless communications devices using downlink MIMO and/or OFDMA. The wireless station receives a plurality of responding frames from the plurality of wireless communications devices concurrently using OFDMA. In one embodiment, the wireless station transmits a MU indication bit and MU bandwidth assignment information in the downlink MIMO and/or OFDMA frames. In another novel aspect, the uplink responding frames from multiple wireless communications devices are sent on a corresponding narrow concurrently over more than one transmission instance. AP polling or SIFS only is used between two transmission instances. When the concurrent responding frames occupies less than a bandwidth of an available uplink OFDMA bandwidth, the unoccupied bandwidth is either left empty or occupied by one or more duplicated responding frames.


Patent
MediaTek Inc. | Date: 2017-07-12

A semiconductor package is provided. The semiconductor package includes a package substrate having a first region and a second region defined between an edge of the package substrate and an edge of the first region. A semiconductor die is disposed on the package substrate in the first region. A three-dimensional (3D) antenna is disposed on the package substrate in the second region. The 3D antenna includes a planar structure portion and a bridge or wall structure portion. A molding compound encapsulates the semiconductor die and at least a portion of the 3D antenna. A conductive shielding element is inside the molding compound or partially covers the molding compound. A semiconductor package assembly having the semiconductor package is also provided.

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