MediaTek Inc.

Hsinchu, Taiwan

MediaTek Inc.

Hsinchu, Taiwan
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A semiconductor package includes a first substrate, a second substrate, a composite solder ball and a first semiconductor component. The composite solder ball includes a core, an encapsulating layer and a barrier layer. The composite solder ball is disposed between the first substrate and the second substrate for electrically connecting the first substrate and the second substrate. The barrier layer is disposed between the core and the encapsulating layer. Wherein a melting point of the barrier layer is higher than a melting point of the core, the melting point of the core is higher than a melting point of the encapsulating layer. The first semiconductor component is disposed between the first substrate and the second substrate.


Methods are provided for concurrent communications among multiple wireless communications devices. In one novel aspect, the wireless station transmits a wideband signal to a plurality of wireless communications devices using downlink MIMO and/or OFDMA. The wireless station receives a plurality of responding frames from the plurality of wireless communications devices concurrently using OFDMA. In one embodiment, the wireless station transmits a MU indication bit and MU bandwidth assignment information in the downlink MIMO and/or OFDMA frames. In another novel aspect, the uplink responding frames from multiple wireless communications devices are sent on a corresponding narrow concurrently over more than one transmission instance. AP polling or SIFS only is used between two transmission instances. When the concurrent responding frames occupies less than a bandwidth of an available uplink OFDMA bandwidth, the unoccupied bandwidth is either left empty or occupied by one or more duplicated responding frames.


The present invention provides a control circuit (1 20) to stabilize an output power of a power amplifier (110). The control circuit (120) comprises a voltage clamping loop (1 30), a current clamping loop (140) and a loop (1 50) for reducing power variation under VSWR, where the voltage clamping loop (1 30) is used to clamp an output voltage of the power amplifier (110) within a defined voltage range, the current clamping loop (140) is used to clamp a current of the power amplifier (110) within a defined current range, and the loop (1 50) for reducing power variation under VSWR is implemented by an impedance detector (1 50) to compensate the output power under VSWR variation.


Patent
MediaTek Inc. | Date: 2017-05-17

An amplifier system (100) includes a main amplifier (110), a cross-over current detector (120) and a controller (130). The main amplifier (110) includes at least a first driving transistor (MD1) and a second driving transistor (MD2) serving as a differential pair, wherein the first driving transistor (MD1) and the second driving transistor (MD2) are arranged to receive a first input signal and a second input signal, respectively. The cross-over current detector (120) is coupled to the main amplifier (110), and is arranged for detecting a cross-over current of the main amplifier (110), wherein the cross-over current of the main amplifier (110) is an overlapped current from the differential pair. The controller (130) is coupled to the main amplifier (110) and the cross-over current detector (120), and is arranged for generating a control signal to control a gain of the main amplifier (110) according to an output of the main amplifier (110) and the cross-over current of the main amplifier (110).


Signaling methods to support robust interference cancellation by obtaining information associated with interfering signals from the network side are provided. The target interference for cancellation is intra-cell interference from Multi-User Multi-Input-Multi-Output (MU-MIMO) or Non-Orthogonal Multiple Access (NOMA) operation. A victim receiver receives both desired signal and intra-cell interfering signal. The network may assist the victim receiver by providing information related to the interfering signal. The computational complexity of the victim receiver in blindly detecting the interfering signal characteristics is reduced, and the reliability of the signal detection is improved.


Patent
MediaTek Inc. | Date: 2017-05-17

A method of direction finding (DF) positioning based on a simplified antenna platform format in a wireless communication network is proposed. A receiver receives antenna platform format information of a transmitter having multiple antenna elements. The antenna platform format information comprises an antenna platform format indicator, antenna platform position and orientation information, a number of antenna elements, and switching delay, phase center, and polarization information for each antenna element. The receiver receives a plurality of direction finding sounding signals transmitted from the transmitter via the multiple antenna elements. The receiver performs a DF algorithm based on the plurality of DF sounding signals and the antenna platform format information and thereby estimating a DF solution. Finally, the receiver determines its own location information based on the estimated DF solution.


Patent
MediaTek Inc. | Date: 2017-05-17

The invention provides a semiconductor package assembly. The semiconductor package assembly includes a redistribution layer (RDL) structure having a first surface and a second surface opposite to the first substrate. The RDL structure includes a redistribution layer (RDL) contact pad arranged close to the second surface. A passivation layer is disposed on the RDL contact pad. The passivation layer has an opening corresponding to the RDL contact pad such that the RDL contact pad is exposed to the opening. A first distance between a first position of the opening and a central point of the opening is different from a second distance between a second position of the opening and the central point of the opening in a plan view.


Patent
MediaTek Inc. | Date: 2017-09-13

A semiconductor device capable of high-voltage operation includes a semiconductor substrate having a first conductivity type. A first well doped region is formed in the semiconductor substrate, having a second conductivity type that is the opposite of the first conductivity type. A first doped region and a second doped region are formed on the first well doped region, having the second conductivity type. A first gate structure is formed over the first well doped region and adjacent to the first doped region. A second gate structure overlaps the first gate structure and the first well doped region. A third gate structure is formed beside the second gate structure and close to the second doped region. The top surface of the first well doped region between the second gate structure and the third gate structure avoids having any gate structure and silicide formed thereon.


Patent
MediaTek Inc. | Date: 2017-09-13

A semiconductor device capable of high-voltage operation includes a semiconductor substrate having a first conductivity type. A first well doped region is formed in a portion of the semiconductor substrate. The first well doped region has a second conductivity type. A first doped region is formed on the first well doped region, having the second conductivity type. A second doped region is formed on the first well doped region and is separated from the first doped region, having the second conductivity type. A first gate structure is formed over the first well doped region and is adjacent to the first doped region. A second gate structure is formed beside the first gate structure and is close to the second doped region. A third gate structure is formed overlapping a portion of the first gate structure and a first portion of the second gate structure.


Patent
MediaTek Inc. | Date: 2017-09-13

A wafer-level chip-size package includes a semiconductor structure. A bonding pad is formed over the semiconductor structure, including a plurality of conductive segments. A conductive component is formed over the semiconductor structure, being adjacent to the bonding pad. A passivation layer is formed, exposing a portions of the conductive segments of the first bonding pad. A conductive redistribution layer is formed over the portions of the conductive segments of the first bonding pad exposed by the passivation layer. A planarization layer is formed over the passivation layer and the conductive redistribution layer, exposing a portion of the conductive redistribution layer. A UBM layer is formed over the planarization layer and the portion of the conductive redistribution layer exposed by the planarization layer. A conductive bump is formed over the UBM layer.

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