Hsinchu City, Taiwan
Hsinchu City, Taiwan

MediaTek Inc. is a fabless semiconductor company that provides system-on-chip solutions for wireless communications, HDTV, DVD and Blu-ray. Headquartered in Hsinchu, Taiwan, the company has 25 offices worldwide and was the 4th largest IC designer worldwide in 2013. Since its founding in 1997, MediaTek has been creating chipset solutions for the global market. MediaTek also provides its customers with reference designs. Wikipedia.


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Patent
MediaTek | Date: 2017-03-08

Techniques related to loading-based dynamic voltage and frequency scaling are described. A method may involve measuring a loading of a first power domain. The first power domain may include one or more circuit sections each of which operating in one of a plurality of loading states. The measuring of the loading of the first power domain may involve determining a respective loading state of each of the one or more circuit sections of the first power domain. The measured loading of the first power domain may be representative of a combination of the one or more loading states of the one or more circuit sections. The method may also involve determining at least one operating parameter of the first power domain according to the measured loading of the first power domain.


Apparatus and methods for sensing current carried by one or more planar conductors is described. A plurality of sensing coils may be fabricated adjacent to one or more planar, current-carrying conductors. The sensing coils may detect a magnetic field generated by time-varying current flowing through the one or more planar conductors. The sensing coils may be arranged to cancel uniform and linear-gradient magnetic fields.


Patent
MediaTek | Date: 2017-03-01

A multi-chip structure comprises a switch system on chip (switch SOC) (110), a plurality of serializer/deserializer (SerDes) chips (120_1-120_4) positioned around the switch SOC (100), and a plurality of inter-chip interfaces (130_1-130_4) for connecting the switch SOC (110) to the plurality of SerDes chips (120_1-1 20_4), respectively.


There is provided a communication receiver comprising: an input for receiving a radio frequency, RF, input signal; and at least one finite impulse response, FIR, discrete time filter, DTF. The at least one FIR DTF comprises: an input circuit comprising an input port for sampling the RF input signal at a sampling frequency that is comparable to the input RF input signal; and N parallel branches, each branch having a set of input unit sampling capacitances, where each unit sampling capacitance is independently selectively coupleable to an output summing node. The input circuit is configured to convert an equivalent input impedance of the at least one FIR DTF around the sampling frequency to a real impedance.


A constant on-time pulse width control-based apparatus (103) capable of detecting a transient event of a voltage converter (100) includes a specific comparator (110), a logic circuit (115), and a controller (105). The specific comparator (110) generates a logic control signal to the logic circuit (115) according to two resultant signals (VC1, VC2) of the controller (105). The logic circuit (115) generates a pulse control signal (Ton) with an on-time pulse width to charge an output capacitor according to the logic control signal. The controller (105) generates the two resultant signals (VC1, VC2) to the specific comparator (110) by generating a voltage ramp signal (Vramp) and amplifying an output voltage ripple signal (Vripple) based on a reference voltage (Vref), and detects the transient event to dynamically adjust the on-time pulse width of the pulse control signal (Ton) according to the amplified output voltage ripple signal (VC1).


A dynamic current sink includes the following elements. A voltage comparator compares a reference voltage with a second control signal from an LDO (Low Dropout Linear Regulator) to generate a first control signal. A first transistor selectively pulls down a voltage at a first node according to the first control signal. The inverter is coupled between the first node and a second node. An NAND gate has a first input terminal coupled to a second transistor and a third node, a second input terminal coupled to the second node, and an output terminal coupled to a fourth node. A capacitor is coupled between the fourth node and a fifth node. A resistor is coupled between the fifth node and a ground voltage. A third transistor has a control terminal coupled to the fifth node, and selectively draws a discharge current from an output node of the LDO.


An apparatus (100, 500, 600) for performing resistance control on a current sensing component (MO) in an electronic device (100, 500, 600) and an associated method are provided. For example, the apparatus (100, 500, 600) may comprise a power switching unit (MO) and a feedback module, and the power switching unit (MO) is utilized as the current sensing component (MO) when the power switching unit (MO) enables the power path. The feedback module may comprise: a power switching unit replica (MS) that receives a first voltage at the battery terminal (VBAT) and outputs a second voltage; a first current source (IA), coupled between the power switching unit replica (MS) and a ground terminal, arranged to receive the second voltage; a reference voltage generator that generates a third voltage; and an error amplifier (110) that receives the second voltage and the third voltage and outputs a fourth voltage, wherein the feedback module controls both of the power switching unit (MO) and the power switching unit replica (MS) according to the fourth voltage.


Examples of front-end modules, apparatuses and methods for coupling compensation in a closed-loop digital pre-distortion (DPD) system are described. The closed-loop DPD circuit (1500) may include a PA (1510) and a loopback path. The PA (1510) may receive a PA input signal and amplify the PA input signal to provide a PA output signal proportional to a product of the PA input signal and a gain of the PA (1510). The loopback path may receive the PA output signal to output a loopback signal. A forward coupling and a backward coupling may exist between the PA input signal and an output of the loopback path. The output of the loopback path may be proportional to a product of the PA output signal and a gain of the loopback path. The loopback path may include a coupling cancellation mechanism (1530) configured to cancel couplings between the PA input signal and the loopback signal.


A computing system performs a policy-based machine code compression method. The computing system hosts a virtual machine that generates machine code from bytecode. The computing system determines whether to compress the machine code file according to a set of conditions specified by a policy. If the set of conditions is satisfied, the machine code file is compressed. For system booting and package installation, the machine code file can be deleted to save storage. When launching an application, the compressed machine code file is decompressed for execution. When the application process terminates, the decompressed machine code file can be deleted. The machine code file compression can be performed on a mobile device to save storage, or on a host when building a system image to reduce download time. Parallel compression and decompression algorithms can be used for the machine code file compression and decompression in a multi-core computing system.


Patent
MediaTek | Date: 2017-03-15

A wireless power transmitter includes a multi-mode drive circuit having a controllable resonant frequency. The multi-mode drive circuit is controlled to have a first resonant frequency to drive wireless power transmission at a first transmit frequency. The multi-mode drive circuit is also controlled to have a second resonant frequency higher than the first resonant frequency to drive wireless power transmission at a second transmit frequency higher than the first transmit frequency.

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