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Newton, MA, United States

A semiconductor device may include a substrate and at least one MOSFET adjacent the substrate. The MOSFET may include a superlattice channel including a plurality of stacked groups of layers, a source and a drain adjacent the superlattice channel, and a gate adjacent the superlattice channel. Each group of layers of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A first dopant may be in at least one region adjacent at least one of the source and drain, and a second dopant may also be in the at least one region. The second dopant may be different than the first dopant and reduce diffusion thereof.


Patent
MEARS Technologies | Date: 2011-01-31

A multiple-wavelength opto-electronic device may include a substrate and a plurality of active optical devices carried by the substrate and operating at different respective wavelengths. Each optical device may include a superlattice comprising a plurality of stacked groups of layers, and each group of layers may include a plurality of stacked semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon.


A semiconductor device may include a substrate, and a plurality of fins spaced apart on the substrate. Each of the fins may include a lower semiconductor fin portion extending vertically upward from the substrate, and at least one superlattice punch-through layer on the lower fin portion. The superlattice punch-through layer may include a plurality of stacked groups of layers, with each group of layers of the superlattice punch-through layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Each fin may also include an upper semiconductor fin portion on the at least one superlattice punch-through layer and extending vertically upward therefrom. The semiconductor device may also include source and drain regions at opposing ends of the fins, and a gate overlying the fins.


A semiconductor device may include an alternating stack of superlattice and bulk semiconductor layers on a substrate, with each superlattice layer including a plurality of stacked group of layers, and each group of layers of the superlattice layer including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include spaced apart source and drain regions in an upper bulk semiconductor layer of the alternating stack of superlattice and bulk semiconductor layers, and a gate on the upper bulk semiconductor layer between the spaced apart source and drain regions.


A semiconductor device may include a substrate, and a plurality of fins spaced apart on the substrate. Each of the fins may include a lower semiconductor fin portion extending vertically upward from the substrate, and at least one superlattice punch-through layer on the lower fin portion. The superlattice punch-through layer may include a plurality of stacked groups of layers, with each group of layers of the superlattice punch-through layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Each fin may also include an upper semiconductor fin portion on the at least one superlattice punch-through layer and extending vertically upward therefrom. The semiconductor device may also include source and drain regions at opposing ends of the fins, and a gate overlying the fins.

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