Entity

Time filter

Source Type

Pacific, WA, United States

Michalas L.,National and Kapodistrian University of Athens | Syntychaki A.,National and Kapodistrian University of Athens | Koutsoureli M.,National and Kapodistrian University of Athens | Papaioannou G.J.,National and Kapodistrian University of Athens | Voutsas A.T.,Material and Device Applications Laboratory
Microelectronics Reliability | Year: 2012

The effect of illumination on the performance of polycrystalline silicon TFTs is investigated by the temperature analysis of the transfer characteristics. The study involved devices fabricated on columnar grain films in order to take also into account the role of material structure. The photosensitivity of devices decreases with increasing temperature and it vanishes above 350 K. Moreover the results suggest that the polycrystalline material microstructure must be taken into account according to the needs of the corresponding applications. © 2012 Elsevier Ltd. All rights reserved. Source


Moschou D.C.,Institute of Microelectronics, Greece | Kontogiannopoulos G.P.,Institute of Microelectronics, Greece | Kouvatsos D.N.,Institute of Microelectronics, Greece | Voutsas A.T.,Material and Device Applications Laboratory
Microelectronics Reliability | Year: 2010

In this work we point out the importance of the device parameter Vg,max-Vth (the difference between the gate voltage at maximum transconductance and the threshold voltage obtained from linear extrapolation method) for LTPS TFTs under dc stress. The evolution of this parameter with stress time is monitored for the first time, along with the other typical device parameters (Vth, Gm,max, S) in order to further clarify the nature of the traps generated. In the first dc stress case considered, we observed very different S degradation of the two samples, but very similar Gm,max degradation, as well as similar Vg,max-Vth evolution. Therefore, Gm,max evolution with stress time was found to be related more strongly to tail state generation, probed through Vg,max-Vth, and not to midgap trap generation, probed through S. In the second case, no midgap state generation is observed, but only severe tail state generation. Hence, the nature of the created defects and the reason for the significant Gm,max reduction could only be probed through the observation of Vg,max-Vth, a parameter not utilized until now. Finally, stressing both n- and p-channel devices, we are able to explain the much more intense Gm,max degradation observed for n-channel devices, associating it to the larger tail state generation in n-channel TFTs, also pointed by Vg,max-Vth evolution with stress. © 2009 Elsevier Ltd. All rights reserved. Source


Moschou D.C.,Institute of Microelectronics, Greece | Kouvatsos D.N.,Institute of Microelectronics, Greece | Pappas I.,Aristotle University of Thessaloniki | Dimitriadis C.,Aristotle University of Thessaloniki | Voutsas A.T.,Material and Device Applications Laboratory
2012 28th International Conference on Microelectronics - Proceedings, MIEL 2012 | Year: 2012

Short channel effects in double gate poly-Si SLS ELA TFTs are studied in this work by electrically characterizing devices with varying top gate length and constant bottom gate length. The electrical parameters were extracted for different bottom gate biases, observing a V th increase with increasing channel length, attributed to more traps present within larger channels. This was also probed through the increase of V g,max-V th with increasing channel length. In order to distinguish between short channel effects and possible L top/L bottom effects, devices with different bottom gate lengths and a constant top gate length were also studied. No similar trends as in the case of decreasing channel length were observed, thus supporting our case that the previously observed behavior is mainly an effect of channel shrinking and not of L top/L bottom effects. © 2012 IEEE. Source


Moschou D.C.,Institute of Microelectronics, Greece | Theodorou C.G.,Aristotle University of Thessaloniki | Hastas N.A.,Aristotle University of Thessaloniki | Tsormpatzoglou A.,Aristotle University of Thessaloniki | And 3 more authors.
IEEE/OSA Journal of Display Technology | Year: 2013

Double-gate (DG) polysilicon thin-film transistors (TFTs) are considered very important for future large area electronics, due to their capability to electrically control TFT characteristics. The scope of this paper is to study how high performance DG polysilicon TFT degradation is affected by shrinking of the channel length. We applied equivalent dc stress in DG TFTs of different top gate length {L}\rm top, with channel width {W} = 8 \ \mum and bottom gate length fixed at {L}-{\rm bot} = 4 \ \mum. Also, to ensure that we only see effects from the top gate operation, the bottom gate bias was kept constant at {-}3 V, pushing the carriers towards the top interface. Degradation seemed to be much more intense in the longer device, despite the scaling of the stress field. This could be attributed to the larger number of sub-boundaries and grain boundaries as {L}\rm top increases, causing larger scattering of the carriers towards the top interface and larger grain-boundary state creation. Low frequency noise measurements support the conclusions regarding the proposed degradation mechanisms of DG polysilicon TFTs with shrinking channel length. © 2005-2012 IEEE. Source


Moschou D.C.,Institute of Microelectronics, Greece | Farmakis F.V.,Institute of Microelectronics, Greece | Kouvatsos D.N.,Institute of Microelectronics, Greece | Voutsas A.T.,Material and Device Applications Laboratory
Microelectronic Engineering | Year: 2012

Utilizing both of the most typical theories for the polysilicon trap energy (monoenergetic traps and traps distributed within the band gap), we prove theoretically that the difference Vg,max - Vth is an electrical parameter reflecting the polysilicon trap density. Through experimental data we verify that this parameter is related differently to the polysilicon nature than other known electrical parameters (Vth, Gm,max), thus providing new information about the film traps. Therefore, with this parameter, we suggest an easy, experimental way to directly evaluate the polysilicon film quality, unavailable till now with the already used parameters. © 2011 Elsevier B.V. All rights reserved. Source

Discover hidden collaborations