Marvell Semiconductors

Pavia, Italy

Marvell Semiconductors

Pavia, Italy

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Radhakrishnan R.,Marvell Semiconductors | Kui C.,Data Storage Institute Singapore
IEEE International Conference on Communications | Year: 2012

In this paper, we introduce an error correction coding scheme, known as reverse concatenated watermark codes for substitution, insertion and deletion channel. This code is obtained by concatenating a distribution transformer with an LDPC code. If the distribution transformer is implemented using a sparsify code then this code is the reverse concatenation of inner and outer codes of the watermark scheme introduced by Davey and Mackay [1]. We show that reverse concatenation significantly decreases decoder complexity and enables an increase in the overall code rate without a prohibitive increase in complexity, although it incurs a loss in performance. © 2012 IEEE.


Byun G.-S.,West Virginia University | Kim Y.,University of California at Los Angeles | Kim J.,Hongik University | Tam S.-W.,Marvell Semiconductors | Chang M.-C.F.,University of California at Los Angeles
IEEE Journal of Solid-State Circuits | Year: 2012

A fully-integrated 8.4 Gb/s 2.5 pJ/b mobile memory I/O transceiver using simultaneous bidirectionaldual band signaling is presented. Incorporating both RF-band and baseband transceiver designs, this prototype demonstrates an energy-efficient and high-bandwidth solution for future mobile memory I/O interface. The proposed amplitude shift keying (ASK) modulator/demodulator with on-chip band-selective transformer obviates a power hungry pre-emphasis and equalization circuitry, revealing a low-power, compact and standard mobile memory-compatible solution. Designed and fabricated in 65-nm CMOS technology, each RF-band and baseband transceiver consumes 10.5 mW and 11 mW and occupies 0.08 mm 2 and 0.06 mm 2 die area, respectively. The dual-band transceiver achieves error-free operation (BER < 10 -15 ) with 2 23-1 PRBS at 8.4 Gb/s over a distance of 10 cm. © 2011 IEEE.


Banerjee G.,Indian Institute of Science | Behera M.,Marvell Semiconductors | Zeidan M.A.,National Instruments | Chen R.,Qualcomm | Barnett K.,Freescale
IEEE Journal of Solid-State Circuits | Year: 2011

A built-in-self-test (BIST) subsystem embedded in a 65-nm mobile broadcast video receiver is described. The subsystem is designed to perform analog and RF measurements at multiple internal nodes of the receiver. It uses a distributed network of CMOS sensors and a low bandwidth, 12-bit A/D converter to perform the measurements with a serial bus interface enabling a digital transfer of measured data to automatic test equipment (ATE). A perturbation/correlation based BIST method is described, which makes pass/fail determination on parts, resulting in significant test time and cost reduction. © 2011 IEEE.


Piotto M.,CNR Institute of Neuroscience | Butti F.,Marvell Semiconductors | Zanetti E.,University of Pisa | Di Pancrazio A.,University of Pisa | And 2 more authors.
Sensors and Actuators, A: Physical | Year: 2015

Acoustic particle velocity sensors have been obtained applying simple low resolution micromachining steps to chips fabricated using a standard microelectronic process. Each sensor consists of four silicided polysilicon wires, suspended over cavities etched into the substrate, and connected to form a Wheatstone bridge. Full compatibility of the micromachining procedure with the original process is demonstrated by integrating a simple pre-amplifier on the same chip as the sensors and showing that both blocks are functional. Proper design of the sensing structures allows them to operate with a single 3.3 V power supply. Sensitivity and noise measurements, performed to estimate the sensor detection limit, are described. Excess noise with a flicker-like behavior, not ascribable to the amplifier, is found when the bridges are biased in working conditions. In addition, the dependence of the sensitivity on the dc bias voltage of the bridges is investigated, comparing the experimental data with the results of a simple analytical model and finite element method simulations. © 2015 Elsevier B.V. All rights reserved.


Piotto M.,CNR Institute of Neuroscience | Butti F.,Marvell Semiconductors | Di Pancrazio A.,University of Pisa | Bruschi P.,University of Pisa
Procedia Engineering | Year: 2014

Novel acoustic particle velocity (APV) sensors suitable for low voltage, battery-powered systems are proposed. The sensing structure consists of four silicide polysilicon wires placed over suspended dielectric membranes and arranged in a Wheatstone full-bridge configuration. The device has been fabricated combining a commercial CMOS process with a simple and low cost post-processing technique. An ultra low noise chopper pre-amplifier has been integrated on the same chip. Preliminary noise and acoustic characterization is presented. © 2014 The Authors. Published by Elsevier Ltd.


Nuzzo P.,IMEC | Nuzzo P.,University of California at Berkeley | Nani C.,Marvell Semiconductors | Armiento C.,University of Pisa | And 4 more authors.
IEEE Transactions on Circuits and Systems I: Regular Papers | Year: 2012

A successive approximation analog-to-digital converter (ADC) architecture is presented that programs its comparator threshold at runtime to approximate the input signal via binary search. While targeting medium resolutions and speed, the threshold configuring (TC) ADC achieves low power consumption and small area occupation by using a fully dynamic configurable comparator and an asynchronous controller, with no need for a highly linear feedback D/A converter. The TC-ADC embeds its own references, and relies on a minimal amount of passive components or calibration loops. A 6-bit prototype implementation in 90-nm digital CMOS technology achieves 32-dB SNDR at 50 MS/s and consumes 240 μW from 1-V analog and 0.7-V digital supplies. This results in 150 fJ/conversion-step in a core area occupation of only 0.0055 mm 2. © 2011 IEEE.


Demissie B.,Fraunhofer Institute for Communication, Information Processing and Ergonomics | Berger C.R.,Marvell Semiconductors
IEEE Transactions on Aerospace and Electronic Systems | Year: 2014

This work contemplates advanced signal processing techniques for narrow band pulsed radar systems. If we assume a sparse scene of point-like targets and formulate the data model for the received signal in Fourier space, we can produce a block sparse estimation problem for the range profile spectra in all relevant Doppler channels. The range profile spectra are jointly estimated by coherent versions of block matching pursuit and basis pursuit algorithms. Then, in each Doppler channel, we compute the delays using a parametric high-resolution method. The mixed sparse/parametric approach overcomes the disadvantages of matched filters concerning resolution and ambiguities and has less computational complexity than full two-dimensional sparse estimation methods. We show results from numerical simulations and experimental measurements recorded with a passive bistatic radar using Global System for Mobil Communications (GSM) base stations as illuminators of opportunity. © 2014 IEEE.


Zhang F.,Marvell Semiconductors | Miyahara Y.,Panasonic | Otis B.P.,University of Washington
IEEE Journal of Solid-State Circuits | Year: 2013

This paper presents a 1.6-mW 2.4-GHz receiver that operates from a single supply of 300 mV allowing direct powering from various energy harvesting sources. We extensively utilize transformer coupling between stages to reduce headroom requirements. We forward-bias bulk-source junctions to lower threshold voltages where appropriate. A single-ended 2.4 GHz RF input is amplified and converted to a differential signal before down-converting to a low IF of 1 to 10 MHz. A chain of IF amplifiers and narrowband filters are interleaved to perform programmable channel selection. The chip is fabricated in a 65-nm CMOS process. The receiver achieves - 91.5-dBm sensitivity for a BER of 10e-3. © 2013 IEEE.


Klumperink E.,University of Twente | Dutta R.,University of Twente | Ru Z.,University of Twente | Nauta B.,University of Twente | Gao X.,Marvell Semiconductors
Proceedings - IEEE International Symposium on Circuits and Systems | Year: 2011

Digital intensive architectures allow for flexibly programmable frequency synthesis. Timing jitter and/or phase noise is an important quality criterion for synthesizers. This paper reviews fundamental limitations for jitter in digital frequency architectures, aiming at finding a basis to compare alternative architectures and optimize jitter performance. It motivates why the product of jitter variance and power consumption is a useful figure of merit (FoM) for optimization, based on fundamental physical limitations. Applying this FoM to multi-phase clock generation leads to the conclusion that circuits with low delay are preferred, favoring a shift register architecture (ring counter) over a Delay Locked Loop. For a PLL a Jitter-Power FoM is also defined and we show that significant improvements have been made during recent years. © 2011 IEEE.


Lollio A.,University of Pavia | Bollati G.,Marvell Semiconductors | Castello R.,University of Pavia
IEEE Journal of Solid-State Circuits | Year: 2010

This paper presents a class G amplifier based on a low distortion switching principle technique called switching currents injection. The switching circuit enables a very smooth handover between the voltage supply rails obtaining both high efficiency and low distortion. An approach for the evaluation of the switching distortion in a class G amplifier (and the ability of the loop to reject it) is proposed and the results obtained are used to optimize the overall distortion after compression by the feedback loop. The integrated 65 nm CMOS class G headphone driver based on the above concept operates from ± 1.4 V and ± 0.35 V supplies. At low power level it uses almost exclusively the low voltage supply reducing the dissipation to 1.63 mW @ P out = 0.5 mW into Ω. At higher power level, where both supplies are used, the smooth transition between the rails allows a THD + N better than - 80 dB for P out ≤ 16 mW into 32 Ω. The SNR is 101 dB, quiescent power is 0.41 mW and active die area is 0.14 mm 2. © 2006 IEEE.

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