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LEUVEN, Belgium

Agency: Cordis | Branch: FP7 | Program: CP | Phase: ICT-2009.3.1 | Award Amount: 4.33M | Year: 2010

The aim of the SQWIRE project is to develop a disruptive, industry-compatible CMOS technology based on novel silicon nanowire transistor structures. The co-ordinator has demonstrated both theoretically and experimentally that nanowire MOS transistors can be fabricated at wafer level using silicon-on-insulator (SOI) substrates. These novel devices have shown electrical properties that are comparable or even superior to those of regular transistors.\nTwo such novel devices are the Gated Resistor (a junctionless transistor simulated, prototype fabricated and patented) and the variable-barrier tunnel transistor (VBT, simulated and patented). To obtain industrial validation, fabrication routes will be developed for these devices on novel 300 mm SOI wafers with silicon film thicknesses of only 10 nm. These routes will be underpinned by process development targeting atom-scale control of the silicon film thickness across the wafer.\nDevice performance will be characterised at die-level and evaluated in a statistically meaningful manner at wafer level. The extracted parameters will serve as the basis for the development of a compact model of the Gated Resistor devices, which can be used for further circuit design and the validation of advanced numerical simulations.\nThe fabrication process for the first device (Gated Resistor) is less complex and more flexible than that of regular transistors. It has the potential of increasing yield and reducing the price of integrated circuits. Furthermore, the Gated Resistor offers the promise of superior scaling to sub-22 nm dimensions compared to regular transistors. In addition, the process can easily be implemented in semiconductor materials other than silicon. The second device (Variable Barrier Transistor) is capable of providing subthreshold slopes sharper than any conventional transistor. This permits one to reduce the supply voltage of integrated circuits, and hence their energy consumption.

Agency: Cordis | Branch: FP7 | Program: CP | Phase: ICT-2007.3.1 | Award Amount: 4.08M | Year: 2008

A big challenge awaits for technological developments to keep up with the demands in the market due to both the large variety of wireless communication channels as well as the fact that they are essentially all used at the same time by widely varying applications. For planned developments of wireless communication channels in the SHF and EHF bands, IC design automation tools are indispensable. These tools are needed to develop nanoscale designs of unprecedented complexity and performance and, in addition, enable the achievement of single-pass design success to avoid costly re-spins and the loss of market opportunities.\nCurrently it is impossible to provide accurate simulations of such a system, or even a smaller section of it encompassing just the RF front-end. The advent of multi-standard and software defined radios requires a new generation of transceiver architectures and corresponding CAD tools. Dealing with centre frequencies in the GHz range, the noise figure is a limitation for state-of-the-art designs. Many transceivers have to work in a mobile environment. Therefore low power consumption is mandatory which must be traded off with the circuits linearity and gain.\nThe key for enabling the realisation of single-chip integration of high-GHz wireless modules is resolving the shortcomings in available design flows. According to the 2006 Sematech roadmap this step in technology requires novel CAD tools and mathematical methods to deal with analogue/digital mixed signal simulation, with challenges in system design and methodologies, parasitic extraction, device and EM simulation, model extraction and optimisation tools. The ICESTARS project will deliver the methodologies and prototype tools to make this possible, by combining the research results of several domains to achieve a clear view on the dependencies between different parts of the complete RF design.

Agency: Cordis | Branch: FP7 | Program: CP | Phase: ICT-2013.3.1 | Award Amount: 5.04M | Year: 2013

Designs in nanoelectronics often lead to problems that are large to simulate and that include strong feedback couplings. Industry demands to include variability to guarantee quality and yield. It also requests to incorporate higher abstraction levels to allow for system simulation in order to shorten design cycles, while preserving accuracy. The nanoCOPS project considers the simulation of two problem classes identified by industry:- Power-MOS devices, with applications in energy harvesting, and which involve couplings between electromagnetics (EM), heat, and stress, and- RF-circuitry in wireless communication, which involves EM-circuits-heat coupling and multirate behaviour, together with analogue-digital signals.Due to the market demands, the scientific challenges are to- create efficient and robust simulation techniques for strongly coupled systems, that exploit the different dynamics of sub-systems and that can deal with signals that differ strongly in the frequency range;- include variability such that robust design, worst case analysis, and yield estimation with tiny failures are possible (including large deviations like 6-sigma);- reduce complexity such that one can still vary parameters and such that the reduced models offer higher abstraction models that are efficient to simulate.Our solutions are- advanced co-simulation/multirate/monolithic techniques, combined with envelope/wavelet approaches;- new generalized techniques from Uncertainty Quantification (UQ) for coupled problems, tuned to the statistical demands from manufacturability;- enhanced, parameterized Model Order Reduction techniques for coupled problems and for UQ.All algorithms will be validated in the industrial design tools provided by our industrial partners.Our consortium covers extensive R&D experience in nanoelectronic IC simulation and complementary expertise. It includes seven universities, one research institute, two large-scale semiconductor companies, and two SMEs.

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