Kwon H.-M.,Chungnam National University |
Han I.-S.,Chungnam National University |
Bok J.-D.,Chungnam National University |
Park S.-U.,Chungnam National University |
And 8 more authors.
IEEE Electron Device Letters | Year: 2011
The behavior of ID random telegraph signal (RTS) noise of a p-MOSFET with an advanced gate stack of HfO2/TaN is experimentally investigated and discussed. The ID-RTS noise is evaluated on a wafer level (100 sites) for statistical evaluation. The observed ratio of I D-RTS noise on a wafer is quite similar to that of a p-MOSFET with the conventional plasma-SiON dielectric, which means that the noise distribution on a wafer level is independent of the gate oxide structure and/or material. However, the relative magnitude of change of the drain current to the applied current (Δ ID/ID) of the p-MOSFETs with high-κ (HK) dielectrics is greater than that of p-MOSFETs with conventional plasma-SiON dielectrics by about six times due to the greater number of preexisting bulk traps in the HK dielectric. Therefore, ID-RTS noise and its associated 1/f noise can present a serious issue to the CMOSFET with an advanced HK dielectric for low-power analog and mixed-signal applications. © 2011 IEEE.
Pang Y.-S.,Magna Chip Semiconductor |
Kim Y.,Magna Chip Semiconductor
Journal of Semiconductor Technology and Science | Year: 2013
A 0.18-μm 3.3 V grounded-gate NMOS (GGNMOS) I/O cell array for timing controller (TCON) application is proposed for improving electrical overstress (EOS) robustness. The improved cell array consists of 20 GGNMOS, 4 inserted well taps, 2 end-well taps and shallow trench isolation (STI). Technology computer-aided design (TCAD) simulation results show that the inserted well taps and extended drain contact gate spacing (DCGS) is effective in preventing EOS failure, e.g. local burnout. Thermodynamic models for device simulation enable us to obtain lattice temperature distributions inside the cells. The peak value of the maximum lattice temperature in the improved GGNMOS cell array is lower than that in a conventional GGNMOS cell array. The inserted well taps also improve the uniformity of turn-on of GGNMOS cells. EOS test results show the validity of the simulation results on improvement of EOS robustness of the new GGNMOS I/O cell array.