San Jose, CA, United States
San Jose, CA, United States

Time filter

Source Type

Kim J.,Sogang University | Han S.,Sogang University | Jewell R.,Magma Design Automation
Journal of Semiconductor Technology and Science | Year: 2010

With scaled technology, timing analysis of circuits becomes more and more difficult. In this paper, we review recently developed circuit simulation techniques created to deal with the cost issues of transistor-level simulations. Various techniques for fast SPICE simulations and Monte Carlo simulations are introduced. Moreover, process and aging variation issues are mentioned, along with promising methodologies.


Wiseguyreports.Com Adds “EDA Software -Market Demand, Growth, Opportunities and analysis of Top Key Player Forecast to 2021” To Its Research Database This report studies sales (consumption) of EDA Software in Global market, especially in United States, China, Europe, Japan, focuses on top players in these regions/countries, with sales, price, revenue and market share for each player in these regions, covering Market Segment by Regions, this report splits Global into several key Regions, with sales (consumption), revenue, market share and growth rate of EDA Software in these regions, from 2011 to 2021 (forecast), like United States China Europe Japan Split by product Types, with sales, revenue, price and gross margin, market share and growth rate of each type, can be divided into Electronic Circuit Design and Simulation Tool PCB Software IC Design Software PLD Design Tools Other EDA Software Split by applications, this report focuses on sales, market share and growth rate of EDA Software in each application, can be divided into Application 1 Application 2 Application 3 Global EDA Software Sales Market Report 2016 1 EDA Software Overview 1.1 Product Overview and Scope of EDA Software 1.2 Classification of EDA Software 1.2.1 Electronic Circuit Design and Simulation Tool 1.2.2 PCB Software 1.2.3 IC Design Software 1.2.4 PLD Design Tools 1.2.5 Other EDA Software 1.3 Application of EDA Software 1.3.1 Application 1 1.3.2 Application 2 1.3.3 Application 3 1.4 EDA Software Market by Regions 1.4.1 United States Status and Prospect (2011-2021) 1.4.2 China Status and Prospect (2011-2021) 1.4.3 Europe Status and Prospect (2011-2021) 1.4.4 Japan Status and Prospect (2011-2021) 1.5 Global Market Size (Value and Volume) of EDA Software (2011-2021) 1.5.1 Global EDA Software Sales and Growth Rate (2011-2021) 1.5.2 Global EDA Software Revenue and Growth Rate (2011-2021) 7 Global EDA Software Manufacturers Analysis 7.1 Cadence (USA) 7.1.1 Company Basic Information, Manufacturing Base and Competitors 7.1.2 EDA Software Product Type, Application and Specification 7.1.2.1 Type I 7.1.2.2 Type II 7.1.3 Cadence (USA) EDA Software Sales, Revenue, Price and Gross Margin (2011-2016) 7.1.4 Main Business/Business Overview 7.2 Mentor Graphics?USA? 7.2.1 Company Basic Information, Manufacturing Base and Competitors 7.2.2 111 Product Type, Application and Specification 7.2.2.1 Type I 7.2.2.2 Type II 7.2.3 Mentor Graphics?USA? EDA Software Sales, Revenue, Price and Gross Margin (2011-2016) 7.2.4 Main Business/Business Overview 7.3 ALTIUM?Australia? 7.3.1 Company Basic Information, Manufacturing Base and Competitors 7.3.2 136 Product Type, Application and Specification 7.3.2.1 Type I 7.3.2.2 Type II 7.3.3 ALTIUM?Australia? EDA Software Sales, Revenue, Price and Gross Margin (2011-2016) 7.3.4 Main Business/Business Overview 7.4 ZUKEN?Japan? 7.4.1 Company Basic Information, Manufacturing Base and Competitors 7.4.2 Nov Product Type, Application and Specification 7.4.2.1 Type I 7.4.2.2 Type II 7.4.3 ZUKEN?Japan? EDA Software Sales, Revenue, Price and Gross Margin (2011-2016) 7.4.4 Main Business/Business Overview 7.5 Synopsys?USA? 7.5.1 Company Basic Information, Manufacturing Base and Competitors 7.5.2 Product Type, Application and Specification 7.5.2.1 Type I 7.5.2.2 Type II 7.5.3 Synopsys?USA? EDA Software Sales, Revenue, Price and Gross Margin (2011-2016) 7.5.4 Main Business/Business Overview 7.6 Magma Design Automation?USA? 7.6.1 Company Basic Information, Manufacturing Base and Competitors 7.6.2 Million USD Product Type, Application and Specification 7.6.2.1 Type I 7.6.2.2 Type II 7.6.3 Magma Design Automation?USA? EDA Software Sales, Revenue, Price and Gross Margin (2011-2016) 7.6.4 Main Business/Business Overview 7.7 Agilent EEsof?USA? 7.7.1 Company Basic Information, Manufacturing Base and Competitors 7.7.2 Software Product Type, Application and Specification 7.7.2.1 Type I 7.7.2.2 Type II 7.7.3 Agilent EEsof?USA? EDA Software Sales, Revenue, Price and Gross Margin (2011-2016) 7.7.4 Main Business/Business Overview 7.8 SpringSoft?China Taiwan? 7.8.1 Company Basic Information, Manufacturing Base and Competitors 7.8.2 Product Type, Application and Specification 7.8.2.1 Type I 7.8.2.2 Type II 7.8.3 SpringSoft?China Taiwan? EDA Software Sales, Revenue, Price and Gross Margin (2011-2016) 7.8.4 Main Business/Business Overview 7.9 ANSYS?USA? 7.9.1 Company Basic Information, Manufacturing Base and Competitors 7.9.2 Product Type, Application and Specification 7.9.2.1 Type I 7.9.2.2 Type II 7.9.3 ANSYS?USA? EDA Software Sales, Revenue, Price and Gross Margin (2011-2016) 7.9.4 Main Business/Business Overview 7.10 Apache Design Solutions?USA? 7.10.1 Company Basic Information, Manufacturing Base and Competitors 7.10.2 Product Type, Application and Specification 7.10.2.1 Type I 7.10.2.2 Type II 7.10.3 Apache Design Solutions?USA? EDA Software Sales, Revenue, Price and Gross Margin (2011-2016) 7.10.4 Main Business/Business Overview 7.11 Applied Wave Research?USA? 7.12 Vennsa Technologies?Canada? 7.13 CIDC?China?


News Article | November 18, 2016
Site: marketersmedia.com

Wiseguyreports.Com Adds “EDA Software -Market Demand, Growth, Opportunities and analysis of Top Key Player Forecast to 2021” To Its Research Database This report studies sales (consumption) of EDA Software in Global market, especially in United States, China, Europe, Japan, focuses on top players in these regions/countries, with sales, price, revenue and market share for each player in these regions, covering Market Segment by Regions, this report splits Global into several key Regions, with sales (consumption), revenue, market share and growth rate of EDA Software in these regions, from 2011 to 2021 (forecast), like United States China Europe Japan Split by product Types, with sales, revenue, price and gross margin, market share and growth rate of each type, can be divided into Electronic Circuit Design and Simulation Tool PCB Software IC Design Software PLD Design Tools Other EDA Software Split by applications, this report focuses on sales, market share and growth rate of EDA Software in each application, can be divided into Application 1 Application 2 Application 3 Global EDA Software Sales Market Report 2016 1 EDA Software Overview 1.1 Product Overview and Scope of EDA Software 1.2 Classification of EDA Software 1.2.1 Electronic Circuit Design and Simulation Tool 1.2.2 PCB Software 1.2.3 IC Design Software 1.2.4 PLD Design Tools 1.2.5 Other EDA Software 1.3 Application of EDA Software 1.3.1 Application 1 1.3.2 Application 2 1.3.3 Application 3 1.4 EDA Software Market by Regions 1.4.1 United States Status and Prospect (2011-2021) 1.4.2 China Status and Prospect (2011-2021) 1.4.3 Europe Status and Prospect (2011-2021) 1.4.4 Japan Status and Prospect (2011-2021) 1.5 Global Market Size (Value and Volume) of EDA Software (2011-2021) 1.5.1 Global EDA Software Sales and Growth Rate (2011-2021) 1.5.2 Global EDA Software Revenue and Growth Rate (2011-2021) 7 Global EDA Software Manufacturers Analysis 7.1 Cadence (USA) 7.1.1 Company Basic Information, Manufacturing Base and Competitors 7.1.2 EDA Software Product Type, Application and Specification 7.1.2.1 Type I 7.1.2.2 Type II 7.1.3 Cadence (USA) EDA Software Sales, Revenue, Price and Gross Margin (2011-2016) 7.1.4 Main Business/Business Overview 7.2 Mentor Graphics(USA) 7.2.1 Company Basic Information, Manufacturing Base and Competitors 7.2.2 111 Product Type, Application and Specification 7.2.2.1 Type I 7.2.2.2 Type II 7.2.3 Mentor Graphics(USA) EDA Software Sales, Revenue, Price and Gross Margin (2011-2016) 7.2.4 Main Business/Business Overview 7.3 ALTIUM(Australia) 7.3.1 Company Basic Information, Manufacturing Base and Competitors 7.3.2 136 Product Type, Application and Specification 7.3.2.1 Type I 7.3.2.2 Type II 7.3.3 ALTIUM(Australia) EDA Software Sales, Revenue, Price and Gross Margin (2011-2016) 7.3.4 Main Business/Business Overview 7.4 ZUKEN(Japan) 7.4.1 Company Basic Information, Manufacturing Base and Competitors 7.4.2 Nov Product Type, Application and Specification 7.4.2.1 Type I 7.4.2.2 Type II 7.4.3 ZUKEN(Japan) EDA Software Sales, Revenue, Price and Gross Margin (2011-2016) 7.4.4 Main Business/Business Overview 7.5 Synopsys(USA) 7.5.1 Company Basic Information, Manufacturing Base and Competitors 7.5.2 Product Type, Application and Specification 7.5.2.1 Type I 7.5.2.2 Type II 7.5.3 Synopsys(USA) EDA Software Sales, Revenue, Price and Gross Margin (2011-2016) 7.5.4 Main Business/Business Overview 7.6 Magma Design Automation(USA) 7.6.1 Company Basic Information, Manufacturing Base and Competitors 7.6.2 Million USD Product Type, Application and Specification 7.6.2.1 Type I 7.6.2.2 Type II 7.6.3 Magma Design Automation(USA) EDA Software Sales, Revenue, Price and Gross Margin (2011-2016) 7.6.4 Main Business/Business Overview 7.7 Agilent EEsof(USA) 7.7.1 Company Basic Information, Manufacturing Base and Competitors 7.7.2 Software Product Type, Application and Specification 7.7.2.1 Type I 7.7.2.2 Type II 7.7.3 Agilent EEsof(USA) EDA Software Sales, Revenue, Price and Gross Margin (2011-2016) 7.7.4 Main Business/Business Overview 7.8 SpringSoft(China Taiwan) 7.8.1 Company Basic Information, Manufacturing Base and Competitors 7.8.2 Product Type, Application and Specification 7.8.2.1 Type I 7.8.2.2 Type II 7.8.3 SpringSoft(China Taiwan) EDA Software Sales, Revenue, Price and Gross Margin (2011-2016) 7.8.4 Main Business/Business Overview 7.9 ANSYS(USA) 7.9.1 Company Basic Information, Manufacturing Base and Competitors 7.9.2 Product Type, Application and Specification 7.9.2.1 Type I 7.9.2.2 Type II 7.9.3 ANSYS(USA) EDA Software Sales, Revenue, Price and Gross Margin (2011-2016) 7.9.4 Main Business/Business Overview 7.10 Apache Design Solutions(USA) 7.10.1 Company Basic Information, Manufacturing Base and Competitors 7.10.2 Product Type, Application and Specification 7.10.2.1 Type I 7.10.2.2 Type II 7.10.3 Apache Design Solutions(USA) EDA Software Sales, Revenue, Price and Gross Margin (2011-2016) 7.10.4 Main Business/Business Overview 7.11 Applied Wave Research(USA) 7.12 Vennsa Technologies(Canada) 7.13 CIDC(China) For more information, please visit https://www.wiseguyreports.com/sample-request/747637-global-eda-software-sales-market-report-2016


Wiseguyreports.Com Adds “EDA Software -Market Demand, Growth, Opportunities and analysis of Top Key Player Forecast to 2021” To Its Research Database This report studies sales (consumption) of EDA Software in Global market, especially in United States, China, Europe, Japan, focuses on top players in these regions/countries, with sales, price, revenue and market share for each player in these regions, covering Market Segment by Regions, this report splits Global into several key Regions, with sales (consumption), revenue, market share and growth rate of EDA Software in these regions, from 2011 to 2021 (forecast), like United States China Europe Japan Split by product Types, with sales, revenue, price and gross margin, market share and growth rate of each type, can be divided into Electronic Circuit Design and Simulation Tool PCB Software IC Design Software PLD Design Tools Other EDA Software Split by applications, this report focuses on sales, market share and growth rate of EDA Software in each application, can be divided into Application 1 Application 2 Application 3 Global EDA Software Sales Market Report 2016 1 EDA Software Overview 1.1 Product Overview and Scope of EDA Software 1.2 Classification of EDA Software 1.2.1 Electronic Circuit Design and Simulation Tool 1.2.2 PCB Software 1.2.3 IC Design Software 1.2.4 PLD Design Tools 1.2.5 Other EDA Software 1.3 Application of EDA Software 1.3.1 Application 1 1.3.2 Application 2 1.3.3 Application 3 1.4 EDA Software Market by Regions 1.4.1 United States Status and Prospect (2011-2021) 1.4.2 China Status and Prospect (2011-2021) 1.4.3 Europe Status and Prospect (2011-2021) 1.4.4 Japan Status and Prospect (2011-2021) 1.5 Global Market Size (Value and Volume) of EDA Software (2011-2021) 1.5.1 Global EDA Software Sales and Growth Rate (2011-2021) 1.5.2 Global EDA Software Revenue and Growth Rate (2011-2021) 7 Global EDA Software Manufacturers Analysis 7.1 Cadence (USA) 7.1.1 Company Basic Information, Manufacturing Base and Competitors 7.1.2 EDA Software Product Type, Application and Specification 7.1.2.1 Type I 7.1.2.2 Type II 7.1.3 Cadence (USA) EDA Software Sales, Revenue, Price and Gross Margin (2011-2016) 7.1.4 Main Business/Business Overview 7.2 Mentor Graphics?USA? 7.2.1 Company Basic Information, Manufacturing Base and Competitors 7.2.2 111 Product Type, Application and Specification 7.2.2.1 Type I 7.2.2.2 Type II 7.2.3 Mentor Graphics?USA? EDA Software Sales, Revenue, Price and Gross Margin (2011-2016) 7.2.4 Main Business/Business Overview 7.3 ALTIUM?Australia? 7.3.1 Company Basic Information, Manufacturing Base and Competitors 7.3.2 136 Product Type, Application and Specification 7.3.2.1 Type I 7.3.2.2 Type II 7.3.3 ALTIUM?Australia? EDA Software Sales, Revenue, Price and Gross Margin (2011-2016) 7.3.4 Main Business/Business Overview 7.4 ZUKEN?Japan? 7.4.1 Company Basic Information, Manufacturing Base and Competitors 7.4.2 Nov Product Type, Application and Specification 7.4.2.1 Type I 7.4.2.2 Type II 7.4.3 ZUKEN?Japan? EDA Software Sales, Revenue, Price and Gross Margin (2011-2016) 7.4.4 Main Business/Business Overview 7.5 Synopsys?USA? 7.5.1 Company Basic Information, Manufacturing Base and Competitors 7.5.2 Product Type, Application and Specification 7.5.2.1 Type I 7.5.2.2 Type II 7.5.3 Synopsys?USA? EDA Software Sales, Revenue, Price and Gross Margin (2011-2016) 7.5.4 Main Business/Business Overview 7.6 Magma Design Automation?USA? 7.6.1 Company Basic Information, Manufacturing Base and Competitors 7.6.2 Million USD Product Type, Application and Specification 7.6.2.1 Type I 7.6.2.2 Type II 7.6.3 Magma Design Automation?USA? EDA Software Sales, Revenue, Price and Gross Margin (2011-2016) 7.6.4 Main Business/Business Overview 7.7 Agilent EEsof?USA? 7.7.1 Company Basic Information, Manufacturing Base and Competitors 7.7.2 Software Product Type, Application and Specification 7.7.2.1 Type I 7.7.2.2 Type II 7.7.3 Agilent EEsof?USA? EDA Software Sales, Revenue, Price and Gross Margin (2011-2016) 7.7.4 Main Business/Business Overview 7.8 SpringSoft?China Taiwan? 7.8.1 Company Basic Information, Manufacturing Base and Competitors 7.8.2 Product Type, Application and Specification 7.8.2.1 Type I 7.8.2.2 Type II 7.8.3 SpringSoft?China Taiwan? EDA Software Sales, Revenue, Price and Gross Margin (2011-2016) 7.8.4 Main Business/Business Overview 7.9 ANSYS?USA? 7.9.1 Company Basic Information, Manufacturing Base and Competitors 7.9.2 Product Type, Application and Specification 7.9.2.1 Type I 7.9.2.2 Type II 7.9.3 ANSYS?USA? EDA Software Sales, Revenue, Price and Gross Margin (2011-2016) 7.9.4 Main Business/Business Overview 7.10 Apache Design Solutions?USA? 7.10.1 Company Basic Information, Manufacturing Base and Competitors 7.10.2 Product Type, Application and Specification 7.10.2.1 Type I 7.10.2.2 Type II 7.10.3 Apache Design Solutions?USA? EDA Software Sales, Revenue, Price and Gross Margin (2011-2016) 7.10.4 Main Business/Business Overview 7.11 Applied Wave Research?USA? 7.12 Vennsa Technologies?Canada? 7.13 CIDC?China?


Ramalingam A.,Magma Design Automation | Singh A.K.,Terra Tech | Nassif S.R.,IBM | Nam G.-J.,IBM | And 2 more authors.
Integration, the VLSI Journal | Year: 2012

Statistical static timing analysis has received wide attention recently and emerged as a viable technique for manufacturability analysis. To be useful, however, it is important that the error introduced in SSTA be significantly smaller than the manufacturing variations being modeled. Achieving such accuracy requires careful attention to the delay models and to the algorithms applied. In this paper, we propose a new sparse-matrix based framework for accurate path-based SSTA, motivated by the observation that the number of timing paths in practice is sub-quadratic based on a study of industrial circuits and the ISCAS89 benchmarks. Our sparse-matrix based formulation has the following advantages: (a) it places no restrictions on process parameter distributions; (b) it can use an accurate polynomial-based delay model which takes into account slope propagation naturally; (c) it takes advantage of the matrix sparsity and high performance linear algebra for efficient implementation. Our experimental results are very promising. © 2011 Elsevier B.V.


Shebaita A.,Magma Design Automation | Das D.,Magma Design Automation | Petranovic D.,Mentor Graphics | Ismail Y.,Northwestern University
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | Year: 2011

A novel methodology for accurate and efficient static timing analysis is presented in this paper. Our methodology uses the traditional cell library table structure with one modification. The cell library tables are filled with the gate output signal moments instead of the gate output 50% delay and output slew. Using only few moments gives much better accuracy and visibility for the gate output waveform than using the time domain information. Simple convolution of the gate output moments with the interconnect moments yields the signal moments at the stage output. The parameters of the gate input signal, which are used for the table access of the successive stage, are directly computed from the predecessor stage output moments using the closed form expressions without having to explicitly transform the frequency domain moments to time domain. Thus, the interconnects and the gates are treated in a unified moment-based homogeneous framework. The proposed approach inherits the classical cell library tables approach efficiency with even reduced computation complexities. As compared to the classical cell library table approach, the proposed approach accounts for the increasingly nonlinear and non-monotonic waveform shapes which are prohibitively difficult to represent in the classical approaches. In contrary to the classical approaches, increasing the accuracy in the novel approach is made flexible and can be achieved by simply using more moments. To illustrate the concept and prove its merits, multiple examples are presented with 2-3 moments which maintain accuracy within 1%-3% as compared to SPICE. © 2011 IEEE.


Rajaram A.,Magma Design Automation | Pan D.Z.,University of Texas at Austin
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | Year: 2010

Clock mesh networks are well known for their variation tolerance. But their usage is limited to high-end designs due to the significantly high resource requirements compared to clock trees and the lack of automatic mesh synthesis tools. Most existing works on clock mesh networks either deal with semi-custom design or perform optimizations on a given clock mesh. However, the problem of obtaining a good initial clock mesh has not been addressed. Also, the problem of achieving a smooth tradeoff between variation tolerance and resource requirements has not been addressed adequately. In this paper, we present our MeshWorks framework, the first comprehensive automated framework for planning, synthesis, and optimization of clock mesh networks that addresses the above issues. Experimental results suggest that our algorithms can achieve an additional reduction of 31% in buffer area, 21% in wirelength, and 23% in power, compared to the best previous work, with similar worst case maximum frequency. We also demonstrate the effectiveness of our framework under several practical issues such as blockages, multiple clocks, uneven load distribution, and electromigration violations. © 2006 IEEE.


Rajaram A.,Magma Design Automation | Pan D.Z.,University of Texas at Austin
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | Year: 2011

Chip-level clock tree synthesis (CCTS) is a key problem that arises in complex system-on-a-chip designs. A key requirement of CCTS is to balance the clock-trees belonging to different IPs such that the entire tree has a small skew across all process corners. Achieving this is difficult because the clock trees in different IPs might be vastly different in terms of their clock structures and cell/interconnect delays. The chip-level clock tree is expected to compensate for these differences and achieve good skews across all corners. Also, CCTS is expected to reduce clock divergence between IPs that have critical timing paths between them. Reducing clock divergence reduces the maximum possible clock skew in the critical paths between the IPs and thus improves yield. This paper proposes effective CCTS algorithms to simultaneously reduce multicorner skew and clock divergence. Experimental results on several test-cases indicate that our methods achieve 30% reduction in the clock divergence with significantly improved multicorner skew variance, at the cost of 2% increase in buffer area and 1% increase in wirelength. © 2011 IEEE.


Venkataraman G.,Magma Design Automation | Feng Z.,Texas A&M University | Hu J.,Texas A&M University | Li P.,Texas A&M University
IEEE Transactions on Very Large Scale Integration (VLSI) Systems | Year: 2010

Clock mesh has been widely used to distribute the clock signal across the chip. Clock mesh is driven by a top-level tree and a set of mesh buffers. We present fast and efficient combinatorial algorithms to simultaneously identify the candidate locations as well as sizes of the buffers driving the clock mesh. We show that such a sizing offers a better solution than inserting buffers of uniform size across the mesh. Due to the high redundancy, a mesh architecture offers high tolerance toward variations in clock skew. However, such a redundancy comes at the expense of mesh wire length and power dissipation. Based on survivable network theory, we formulate the problem to reduce the clock mesh by retaining only those edges that are critical to maintain redundancy. Such a formulation offers designer the option to tradeoff between power and tolerance to process variations. We present efficient postprocessing techniques to reduce the size of the mesh buffers after mesh reduction. Experimental results indicate that our techniques can result in power savings up to 28% with less than 3.3% delay penalty. We also present driver models that can help in simulating the clock mesh. Such models achieve near-HSPICE accuracy with significant speedup in run time. © 2009 IEEE.


Rubanov N.,Magma Design Automation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | Year: 2011

As integrated circuit technologies are scaled down to the nanometer regime, process variations have increasing impact on circuit timing. To address this issue, parameterized statistical static timing analysis (SSTA) has been recently developed. In parameterized SSTA, process variations are represented as random variables (RVs) and timing quantities (delays and others) are expressed as functions of these variables. Most of the existing algorithms to compute the MAX/MIN operations in parameterized SSTA model spatial and path-based statistical dependencies of variation sources using the second-order statistical methods. Unfortunately, such methods have limited capabilities to determine statistical relations between RVs. This results in decreasing the accuracy of the MAX/MIN algorithms, especially when process parameters follow non-Gaussian probability density functions (PDFs) and/or affect timing quantities nonlinearly. In contrast, information theory (IT) provides powerful techniques that allow a natural PDF-based analysis of probabilistic relations between RVs. So, in this paper, we propose a new framework to perform the MAX/MIN operations based on IT concepts. The key ideas behind our framework are: 1) exploiting information entropy to measure unconditional equivalence between an actual MAX/MIN output and its approximate parameterized representation, and 2) using mutual information to measure equivalence of actual and parameterized MAX/MIN outputs from the viewpoint of their statistical relations to process variations. We construct a general IT-based MAX/MIN algorithm that allows a number of particular realizations accounting for statistical properties of parameterized RVs. The experimental results validate the correctness and demonstrate a high accuracy of the new IT-based approach to compute the MAX/MIN. © 2011 IEEE.

Loading Magma Design Automation collaborators
Loading Magma Design Automation collaborators