Lu C.-Y.,Macronix International Co.
Journal of Nanoscience and Nanotechnology | Year: 2012
NAND Flash memory has scaled at phenomenal speed in the last decade and conventional floating gate (FG) Flash memory has now commenced volume production in the 2X nm node. Despite this stunning success, the technology challenges are formidable below 20 nm. Charge-trapping (CT) devices are promising to scale beyond 20 nm but below 10 nm both CT and FG devices hold too few electrons for robust MLC (Multi-level Cell, or more than one bit storage per cell) storage. The simpler structure and its more robust storage (not sensitive to tunnel oxide defects since charges are stored in deep trap levels) also make CT suitable for 3D stacking. Optimistically, 3D CT Flash memory may allow the density increase to continue for at least another decade beyond the 1X nm node. In this paper, we review the current status of FG devices, their scaling challenges, and the operation principles of CT devices and several variations such as TANOS and BE-SONOS. We will then discuss various 3D memory architectures, technology challenges and address the poly-silicon thin film transistor (TFT) issues. Copyright © 2012 American Scientific Publishers. All rights reserved. Source
Macronix International Co. | Date: 2015-01-06
A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as strings which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit line structures at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines.
Macronix International Co. | Date: 2015-01-20
A semiconductor device, in particular, an extended drain metal oxide semiconductor (ED-MOS) device, defined by a doped shallow drain implant in a drift region. For example, an extend drain n-channel metal oxide semiconductor (ED-NMOS) device is defined by an n doped shallow drain (NDD) implant in the drift region. The device is also characterized by conductive layer separated from a substrate in part by a thin oxide layer and in another part by a thick/thin oxide layer. A method of fabricating a semiconductor device, in particular an ED-NMOS device, having a doped shallow drain implant of a drift region is also provided. A method is also provided for fabricating conductive layer disposed in part across a thin oxide layer and in another part across a thick/thin oxide layer.
Macronix International Co. | Date: 2015-08-24
The storage layer such as a nitride layer of a nonvolatile memory cell has two storage parts storing separately addressable data, typically respectively proximate to the source terminal and the drain terminal. The applied drain voltage while sensing the data of one of the storage parts depends on the data stored at the other storage part; the different parts can be in different, neighboring memory cells. If the data stored at the other storage part is represented by a threshold voltage exceeding a minimum threshold voltage, then the applied drain voltage is raised. This technology is useful in read operations and program verify operations to widen the threshold voltage window.
Macronix International Co. | Date: 2015-03-25
A method is provided for operating a NAND array that includes a plurality of blocks of memory cells. A block of memory cells in the plurality of blocks includes a plurality of NAND strings having channel lines between first string select switches and second string select switches. The plurality of NAND strings shares a set of word lines between the first and second string select switches. A channel-side erase voltage is applied to the channel lines through the first string select switches in a selected block. Word line-side erase voltages are applied to a selected subset including more than one member of the set of word lines shared by NAND strings in the selected block to induce tunneling in memory cells coupled to the selected subset, while tunneling is inhibited in memory cells coupled to an unselected subset including more than one member of the set of word lines.