Macronix International Co.

Hsinchu, Taiwan

Macronix International Co.

Hsinchu, Taiwan
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Patent
Macronix International Co. | Date: 2017-01-11

A stacked non-volatile memory device (100) comprises a plurality of bitline (110) and wordline (120) layers stacked on top of each other. The bitline (110) layers comprise a plurality of bitlines that can be formed using advanced processing techniques making fabrication of the device efficient and cost effective. The device can be configured for NAND operation.


Patent
Macronix International Co. | Date: 2016-04-08

A data allocating method includes steps of: determining whether data to be written into a physical memory block is hot data or cold data; when the data is hot data, according to a hot data allocating order, searching at least one first empty sub-block from the physical memory block to allocate the data; when the data is cold data, according to a cold data allocating order, searching at least one second empty sub-block from the physical memory block to allocate the data.


Patent
Macronix International Co. | Date: 2016-11-07

A memory device, which can be configured as a 3D NAND flash memory, includes a plurality of stacks of conductive strips, including even stacks and odd stacks having sidewalls. Some of the conductive strips in the stacks are configured as word lines. Data storage structures are disposed on the sidewalls of the even and odd stacks. Active pillars between corresponding even and odd stacks of conductive strips include even and odd semiconductor films connected at the bottom of the trench between the stacks, and have outside surfaces and inside surfaces. The outside surfaces contact the data storage structures on the sidewalls of the corresponding even and odd stacks forming a 3D array of memory cells; the inside surfaces are separated by an insulating structure that can include a gap. The semiconductor films can be thin-films having a U-shaped current path.


Patent
Macronix International Co. | Date: 2016-11-30

A memory structure includes N array regions and N page buffers coupled to the N array regions, respectively. N is an integer2. Each of the N array regions includes a 3D array of a plurality of memory cells. The memory cells have a lateral distance d between two adjacent memory cells on a horizontal cell plane of the 3D array. Each of the N array regions further includes a plurality of conductive lines. The conductive lines are disposed over and coupled to the 3D array. The conductive lines have a pitch p, and p/d=1/5 to 1/2. The N array regions and the N page buffers are arranged on one line along an extension direction of the conductive lines. M array regions of the N array regions are configured to operate simultaneously. M is an integer. M/N=1/2 or 1.


Patent
Macronix International Co. | Date: 2016-11-15

Semiconductor devices are provided having large vias, such as under bonding pads, to increase the via open area ratio, increase the via etching rate, and avoid inter-metal dielectric cracking and damage to the integrated circuit. The via is defined as a large open area in the inter-metal dielectric layer between an isolated conductive bottom substrate layer and a conductive top layer. Methods of manufacturing semiconductor devices with a large via are also provided.


Patent
Macronix International Co. and Ibm | Date: 2016-02-24

A write pulse driver is provided. The write pulse driver includes a parameter storage, storing a set of parameters specifying characteristics of a write pulse, and driver circuitry configured to generate the write pulse on an output node, the write pulse having a leading edge, a trailing edge and an intermediate segment between the leading edge and the trailing edge, wherein the driver circuitry includes pulse shaping circuits that set shape characteristics of at least one of an amplitude, a duration and a slope of more than one of the leading edge, the trailing edge and the intermediate segment of the write pulse using the set of parameters.


Patent
Macronix International Co. and Ibm | Date: 2016-07-28

A memory configured to have data read therefrom is provided. The memory includes a data port including B transmitters disposed in parallel and for transferring data on both rising and falling edges of a clock, a first memory including a first data bus including N lines on which N bits can be transferred, and a second memory including a second data bus including N lines on which N bits can be transferred. The memory includes a data path controller including a data distributor disposed between the first and second memories and being connected to the data port, wherein, on the rising edge, the data distributor distributes a first data segment comprised of B bits from the first data bus to the data port and, on the falling edge, the data distributor distributes a second data segment comprised of B bits from the second data bus to the data port.


Counting status circuits are electrically coupled to corresponding status elements. The status elements selectably store a bit status of a bit line coupled to a memory array. The bit status can indicate one of at least pass and fail. The counting status circuits are electrically coupled to each other in a sequential order. Control logic causes processing of the counting status circuits in the sequential order to determine a total of the memory elements that store the bit status. The total number of memory elements that store the bit status indicate the number of error bits or non-error bits, which can help determine whether there are too many errors to be fixed by error correction codes.


Patent
Macronix International Co. | Date: 2016-07-20

A memory system has a plurality of memory devices coupled with a hub in discrete and shared port arrangements. A plurality of bus lines connect the plurality of memory devices to the hub, including a first subset of bus lines connected in a point-to-point configuration between the hub and a particular memory device, and a second subset of bus lines connected to all the memory devices in the plurality of memory devices including the particular memory device. Bus operation logic is configured to use the first subset of bus lines in a first operation accessing the particular memory device while simultaneously using the second subset of bus lines in a second operation accessing a different selected memory device of the plurality of memory devices.


Patent
Macronix International Co. | Date: 2016-01-14

A method and a device for performing a polar codes channel-aware procedure are provided. A plurality of bit-channels have a polar code construction which is dynamic. The method includes the following steps. A plurality of reliability indices of some of the bit-channels are ranked. Whether an updating condition is satisfied is determined according to a ranking sequence of the reliability indices. If the updating condition is satisfied, the polar code construction is updated according to the ranking sequence of the reliability indices.

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