Hsinchu, Taiwan
Hsinchu, Taiwan

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Patent
Macronix International Co. and Ibm | Date: 2016-02-24

A write pulse driver is provided. The write pulse driver includes a parameter storage, storing a set of parameters specifying characteristics of a write pulse, and driver circuitry configured to generate the write pulse on an output node, the write pulse having a leading edge, a trailing edge and an intermediate segment between the leading edge and the trailing edge, wherein the driver circuitry includes pulse shaping circuits that set shape characteristics of at least one of an amplitude, a duration and a slope of more than one of the leading edge, the trailing edge and the intermediate segment of the write pulse using the set of parameters.


Patent
Macronix International Co. and Ibm | Date: 2016-07-28

A memory configured to have data read therefrom is provided. The memory includes a data port including B transmitters disposed in parallel and for transferring data on both rising and falling edges of a clock, a first memory including a first data bus including N lines on which N bits can be transferred, and a second memory including a second data bus including N lines on which N bits can be transferred. The memory includes a data path controller including a data distributor disposed between the first and second memories and being connected to the data port, wherein, on the rising edge, the data distributor distributes a first data segment comprised of B bits from the first data bus to the data port and, on the falling edge, the data distributor distributes a second data segment comprised of B bits from the second data bus to the data port.


Patent
Macronix International Co. | Date: 2016-11-30

A memory structure includes N array regions and N page buffers coupled to the N array regions, respectively. N is an integer2. Each of the N array regions includes a 3D array of a plurality of memory cells. The memory cells have a lateral distance d between two adjacent memory cells on a horizontal cell plane of the 3D array. Each of the N array regions further includes a plurality of conductive lines. The conductive lines are disposed over and coupled to the 3D array. The conductive lines have a pitch p, and p/d=1/5 to 1/2. The N array regions and the N page buffers are arranged on one line along an extension direction of the conductive lines. M array regions of the N array regions are configured to operate simultaneously. M is an integer. M/N=1/2 or 1.


Patent
Macronix International Co. | Date: 2016-11-07

A memory device, which can be configured as a 3D NAND flash memory, includes a plurality of stacks of conductive strips, including even stacks and odd stacks having sidewalls. Some of the conductive strips in the stacks are configured as word lines. Data storage structures are disposed on the sidewalls of the even and odd stacks. Active pillars between corresponding even and odd stacks of conductive strips include even and odd semiconductor films connected at the bottom of the trench between the stacks, and have outside surfaces and inside surfaces. The outside surfaces contact the data storage structures on the sidewalls of the corresponding even and odd stacks forming a 3D array of memory cells; the inside surfaces are separated by an insulating structure that can include a gap. The semiconductor films can be thin-films having a U-shaped current path.


Patent
Macronix International Co. | Date: 2016-11-15

Semiconductor devices are provided having large vias, such as under bonding pads, to increase the via open area ratio, increase the via etching rate, and avoid inter-metal dielectric cracking and damage to the integrated circuit. The via is defined as a large open area in the inter-metal dielectric layer between an isolated conductive bottom substrate layer and a conductive top layer. Methods of manufacturing semiconductor devices with a large via are also provided.


Patent
Macronix International Co. | Date: 2017-01-11

A stacked non-volatile memory device (100) comprises a plurality of bitline (110) and wordline (120) layers stacked on top of each other. The bitline (110) layers comprise a plurality of bitlines that can be formed using advanced processing techniques making fabrication of the device efficient and cost effective. The device can be configured for NAND operation.


Patent
Macronix International Co. | Date: 2016-03-18

A memory device comprising a conglomerate material interposed between a first electrode and a second electrode is provided. The conglomerate material includes nanocrystalline grains embedded in an amorphous matrix. During operations, phase change reactions occur at the inter-grain boundaries in the conglomerate material so as to reduce the operation power.


Patent
Macronix International Co. | Date: 2016-05-18

A NAND-based non-volatile memory contact structure includes a trench located adjacent to layered alternating conducting and insulating layers, the layers lining sides and bottom of the trench. A portion of the trench is removed to expose a surface in which electrical connections to the conducting layers are provided on one level.


Patent
Macronix International Co. | Date: 2016-02-17

A method is provided for operating a NAND array that includes a plurality of blocks of memory cells. A block of memory cells in the plurality of blocks includes a plurality of NAND strings having channel lines between first string select switches and second string select switches. The plurality of NAND strings shares a set of word lines between the first and second string select switches. A channel-side erase voltage is applied to the channel lines through the first string select switches in a selected block. Word line-side erase voltages are applied to a selected subset including more than one member of the set of word lines shared by NAND strings in the selected block to induce tunneling in memory cells coupled to the selected subset, while tunneling is inhibited in memory cells coupled to an unselected subset including more than one member of the set of word lines.


Patent
Macronix International Co. | Date: 2016-06-17

An erasing method of a memory device is provided. The memory device includes a memory controller and a memory array having a first memory region and a second memory region. The first memory region and the second memory region share the same well. The erasing method comprising steps of: erasing the first memory region; and selectively programming the second memory region according to an error correction code algorithm.

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