Lyon Institute of Nanotechnology

Villeurbanne, France

Lyon Institute of Nanotechnology

Villeurbanne, France
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Filiol H.,Mentor Graphics | O'Connor I.,Lyon Institute of Nanotechnology | Morche D.,CEA Grenoble
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | Year: 2012

In nanoscale integrated circuit technologies, process parameter fluctuations gain increasingly in importance. Efficient methods are thus required during the design phase to evaluate the resulting variability. In this letter, we propose a new method to estimate the variation bounds of analog circuit performance. This method combines design of experiment techniques with the Cornish-Fisher expansion: process parameter variations are first mapped to circuit performance metrics by a quadratic model, and then an analytical approximation of the performance distribution's quantiles enables the enclosure of the performance variations. The proposed method demonstrates a better accuracy/efficiency ratio than Monte-Carlo-based methods. © 2012 IEEE.

O'Connor I.,École Centrale Lyon | Liu J.,École Centrale Lyon | Navarro D.,École Centrale Lyon | Daviot R.,Lyon Institute of Nanotechnology | And 3 more authors.
International Journal of Nanotechnology | Year: 2010

This paper describes a reprogrammable architecture based on regular matrices of fine-grain dynamically reconfigurable cells based on double-gate carbon nanotube field effect transistors (DG-CNTFET) exhibiting ambivalence (p-type or n-type behaviour depending on the back-gate voltage). Using available models, reconfigurable cells have been simulated and performance metrics quantified at 4 GHz operation. A function mapping method suitable for this matrix structure has been devised, and various interconnect topologies have been analysed, showing average mapping success rates to 4 × 4 cell matrices of above 80% for 8-node function graphs. This gives insight into the way data functionality could be coded into the architecture based on such reconfigurable cells for on-the-fly and partial reprogrammability. Copyright © 2010 Inderscience Enterprises Ltd.

Duong L.H.K.,Hong Kong University of Science and Technology | Nikdast M.,Ecole Polytechnique de Montréal | Xu J.,Hong Kong University of Science and Technology | Wang Z.,Hong Kong University of Science and Technology | And 4 more authors.
Proceedings -Design, Automation and Test in Europe, DATE | Year: 2015

Recently, optical interconnects have been proposed for ultra-high bandwidth and low latency inter/intra-chip communication in multiprocessor systems-on-chip (MPSoCs). These optical interconnects employ the microresonators (MRs) to direct/detect the optical signal. However, utilized MRs suffer from intrinsic crosstalk noise and power loss, degrading the network efficiency via the signal-to-noise ratio (SNR). In this paper, both coherent and incoherent crosstalk in wavelength-division multiplexing (WDM) networks are discussed and systematically analyzed. We carefully develop our analytical models at the optical-circuit level, and apply them to two ring-based networks: SUOR and Corona ONoCs. The quantitative results have demonstrated that the architectural design of the ONoCs determines the impact of crosstalk on the SNR. Even though SUOR and Corona are both ring-based ONoCs, the worst-case SNR can be differed up to 50dB. Our analyses of the worst-case SNR can be utilized as a platform to compare the realistic performance among different optical interconnection networks via the degradation of BER and data bandwidth. © 2015 EDAA.

Channoufi M.,SERCOM Laboratory of Electronic Systems and Communication Networks | Channoufi M.,Cergy-Pontoise University | Lecoy P.,Cergy-Pontoise University | Le-Beux S.,Lyon Institute of Nanotechnology | And 2 more authors.
Optoelectronics and Advanced Materials, Rapid Communications | Year: 2014

The next generation of multiprocessor systems on chip requires development and improvement of innovative implementations of optical networks on chip (ONoC). ONoC efficiency mostly relies on crosstalk between waveguides and on optical power loss. Taking into account new integration capabilities in order to achieve the best design compromise minimizing power loss and crosstalk is thus mandatory. In this paper, we propose a novel switch implementation based upon a multi-layer microring resonator, allowing efficient light coupling and switching between superposed waveguides. Such microring resonator avoids waveguide crossing, thus contributing to reduce propagation losses. A transmission loss from -4.8 to -7 dB, crosstalk between -17 and -29 dB, a quality factor about 202 allowing a bandwidth up to 1THz, are demonstrated with a 1.65 μm radius microring. Furthermore, this paper demonstrates that pure curvature loss remains less than -0.4 dB for microring radii less than 2μm thus allowing miniaturization of switch size.

Cao R.,Mentor Graphics | Couder L.,Mentor Graphics | Cayo J.,Mentor Graphics | Ferguson J.,Mentor Graphics | And 3 more authors.
2014 IEEE Optical Interconnects Conference, OI 2014 | Year: 2014

We discuss why electronic design automation tools need new functionality to perform curvilinear layout feature validation of photonic integrated circuits. We evaluate and test different algorithms for curvilinear path length and curvature measurement. © 2014 IEEE.

Russo P.,Lyon Institute of Nanotechnology | Pillonnet G.,Lyon Institute of Nanotechnology | Abouchi N.,Lyon Institute of Nanotechnology | Taupin S.,Analog and Power Management Business Unit | Goutti F.,Analog and Power Management Business Unit
133rd Audio Engineering Society Convention 2012, AES 2012 | Year: 2012

Class G amplifiers arc an effective solution to increase the audio efficiency for headphone applications, but realistic operating conditions have to be taken into account to predict and optimize power efficiency. In fact, power supply tracking, which is a key factor for high efficiency, is poorly optimized with the classical design method, becausc the stimulus used is very different from a real audio signal. Here, a methodology has been proposed to find class G nominal conditions. By using relevant stimuli and nominal output power, the simulation and test of the class G amplifier are closer to the real conditions. Moreover, a novel simulator is used to quickly evaluate the efficiency with these long duration stimuli, i.e. ten seconds instead of a few milliseconds. This allows longer transient simulation for an accurate efficiency and audio quality evaluation by averaging the Class G behavior. Based on this simulator, this paper indicates the limitations of the well-established test setup. Real efficiencies vary up to ±50% from the classical methods. Finally, the study underlines the need to use real audio signals to optimize the supply voltage tracking of Class G amplifiers in order to achieve a maximal efficiency in nominal operation.

Huffenus A.,Lyon Institute of Nanotechnology | Pillonnet G.,Lyon Institute of Nanotechnology | Abouchi N.,Lyon Institute of Nanotechnology | Goutti F.,STMicroelectronics
128th Audio Engineering Society Convention 2010 | Year: 2010

This paper compares two modulation schemes for Class-D amplifiers: Phase-Shift Self-Oscillating (PSSO) and Carrier-Based Pulse Width Modulation (PWM). Theoretical analysis (modulation, frequency of oscillation, bandwidth...), design procedure, and IC silicon evaluation will be shown for mono and stereo operation (on the same silicon die) on both structures. The design of both architectures will use as many identical building blocks as possible, to provide a fair, "all else being equal", comparison. THD+N performance and idle consumption went from 0.02% and 5.6mA in PWM to 0.007% and 5.2mA in Self-Oscillating. Other advantages and drawbacks of the Self-Oscillating structure will be explained and compared to the classical Carrier-Based PWM one, with a focus on battery-powered applications.

Huffenus A.,Lyon Institute of Nanotechnology | Pillonnet G.,Lyon Institute of Nanotechnology | Abouchi N.,Lyon Institute of Nanotechnology | Goutti F.,STMicroelectronics | And 2 more authors.
ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems | Year: 2010

This paper presents a highly efficient stereo audio amplifier, based on a self-oscillating modulator. This modulation scheme has been analyzed and shows to have a higher bandwidth and error correction than standard Pulse Width Modulation (PWM). A practical implementation in CMOS 0.25um technology has been done to validate our theoretical and simulation results, based on a modified PWM amplifier. Our amplifier demonstrated a Total Harmonic Distortion plus Noise (THD+N) as low as 0.007%, current consumption is 3.88mA at 3.6V (stereo) and the efficiency reaches 88% into 8Ohms. The integrated circuit measures 1.6x1.6mm and is able to work at supply voltages from 2.3V to 5.5V. ©2010 IEEE.

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