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San Jose, CA, United States

LSI Corporation was an electronics company based in San Jose, California that designed semiconductors and software that accelerate storage and networking in datacenters, mobile networks and client computing.On May 6, 2014, LSI Corporation was acquired by Avago Technologies for $6.6 billion. LSI Stockholders voted in favor of the proposal in April 2014, merging the company into its parent. Wikipedia.


Patent
LSI Corporation | Date: 2014-01-13

An SRAM device includes a segmented memory cell array with a plurality of memory cells. Each segment of memory cells includes a bitline coupled to the memory cells in the segment. The SRAM device further includes a global bitline traversing the segmented memory cell array and communicatively coupled to the memory cell segments via the local bitlines for writing to the memory cells. The SRAM device further includes a global input/output module operable to hold the global bitline at logical zero, to toggle the global bitline to logical one when data is to be written, to select one of the segments of memory cells for writing after the global bitline has been toggled, and to toggle the global bitline to logical zero when data is written to the selected memory cell segment to provide a negative boost voltage to the local bitline of the selected memory cell segment.


An image processing system comprises an image processor having image processing circuitry and an associated memory. The image processor is configured to implement a gesture recognition system comprising a static pose recognition module. The static pose recognition module is configured to identify a region of interest in at least one image, to represent the region of interest as a segmented region of interest comprising a union of segment sets from respective ones of a plurality of lines, to estimate features of the segmented region of interest, and to recognize a static pose of the segmented region of interest based on the estimated features. The lines from which the respective segment sets are taken illustratively comprise respective parallel lines configured as one of horizontal lines, vertical lines and rotated lines. A given one of the segments in one of the sets may be represented by a pair of segment coordinates.


Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional IC design, (2) determining a target clock rate for the functional IC design, (3) synthesizing a netlist from the functional IC design that meets the target clock rate, (4) determining a performance/power ratio from the netlist, (5) attempting to increase the performance/power ratio by changing at least one of a speed, an area and a power consumption in at least some noncritical paths in the netlist, and (6) implementing a layout of the IC from the netlist.


Patent
LSI Corporation | Date: 2014-06-16

In one embodiment, a scheme for reliably reading data values, such as rapidly-changing counter values, from a memory location. Instead of performing a single read operation, a set of N consecutive read operations is performed to obtain a set of N samples. Since, for counter values and the like, the frequency of occurrence of out-of-sequence values is relatively low, it is expected that a majority of the N samples will be in sequence. Of these N samples, the largest subset of monotonically-increasing values is selected. The median value of this subset of monotonically non-decreasing values is returned as a reliable result of the read operation.


Patent
LSI Corporation | Date: 2014-02-14

Higher-level redundancy information computation enables a Solid-State Disk (SSD) controller to provide higher-level redundancy capabilities to maintain reliable operation in a context of failures of non-volatile (e.g. flash) memory elements during operation of an SSD. A first portion of higher-level redundancy information is computed using parity coding via an XOR of all pages in a portion of data to be protected by the higher-level redundancy information. A second portion of the higher-level redundancy information is computed using a weighted-sum technique, each page in the portion being assigned a unique non-zero index as a weight when computing the weighted-sum. Arithmetic is performed over a finite field (such as a Galois Field). The portions of the higher-level redundancy information are computable in any order, such as an order based on order of read operation completion of non-volatile memory elements.

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