Low Power Electronics Association and Project LEAP

Tsukuba, Japan

Low Power Electronics Association and Project LEAP

Tsukuba, Japan
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Masuhara T.,Low Power Electronics Association and Project LEAP
2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011 | Year: 2011

Future society requires networking of efficient portable, wearable, implantable IT/electronics and sensors for mobile, healthcare, smart grid and robot services. Power of small terminals operated by batteries or energy harvesting means, obviously need to be reduced. Power of data centers with much more processing capability and storage capacity compared to those now, also need to be reduced. Challenge toward low-voltage and low-power direction is, therefore, becoming increasingly important in future integrated circuits. © 2011 IEEE.


Sugii N.,Low power Electronics Association and Project LEAP
Proceedings - IEEE International SOI Conference | Year: 2011

• Ultralow-power CMOS should be operated under E min condition in principle. • Compromise between E and speed is done with adaptive V dd and V b control. • Reducing RDF variability and back-bias control is a key requirement for ULV-operation CMOS. SOTB is the suitable device structure for this purpose. • From ULP application viewpoint, ULP wireless communication and power source are crucial issues as well as ULV LSIs. • "Perpetuum Mobile" microcomputer awaits vast new application field. © 2011 IEEE.


Sugii N.,Low power Electronics Association and Project LEAP
Microelectronic Engineering | Year: 2015

Scaling the CMOS device has continuously improved its functionality and performance while lowering its power consumption and price. However, the current "scaled CMOS" technology faces several problems regarding power consumption, and a migration to new transistor structures is proceeding. "Fully depleted silicon on insulator" (FDSOI) technology can lower power consumption and improve performance of CMOS circuits with a capability of low-voltage operation. This article reviews advances in FDSOI technology: device structure, back-bias control function, fabrication process, demonstration of small variability of transistors, reliability including soft error, low voltage circuit design and silicon verification, and improvement in the energy efficiency of CMOS logic circuits. The strong requirement of further improvement in energy in the near future is finally pointed out. © 2014 Elsevier B.V. All rights reserved.


Umeki Y.,Kobe University | Yanagida K.,Kobe University | Yoshimoto S.,Kobe University | Izumi S.,Kobe University | And 4 more authors.
Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013 | Year: 2013

This paper exhibits a 65-nm 8-Mb spin transfer torque magnetoresistance random access memory (STT-MRAM) operating at a single supply voltage with a process-variation tolerant sense amplifier. The proposed sense amplifier comprises a boosted-gate nMOS and negative-resistance pMOSes as loads, which maximizes the readout margin in any process corner. The STT-MRAM achieves a cycle time of 1.9 μs (= 0.526 MHz) at 0.38 V. The operating power is 6.15 μW at that voltage. The minimum energy per access is 3.89 pJ/bit when the supply voltage is 0.44 V. The proposed STT-MRAM operates at lower energy than SRAM when a utilization of a memory bandwidth is 14% or less. © 2013 IEEE.


Yoshida C.,Low power Electronics Association and Project LEAP | Ochiai T.,Low power Electronics Association and Project LEAP | Iba Y.,Low power Electronics Association and Project LEAP | Yamazaki Y.,Low power Electronics Association and Project LEAP | And 3 more authors.
Digest of Technical Papers - Symposium on VLSI Technology | Year: 2012

We engineered the interface of the MgO barrier prepared by post-oxidation of Mg metal to improve structural and electronic properties of magnetic tunnel junctions (MTJs). Drastic improvements in magnetoresistance ratio (MR) and switching voltage (V c) with low resistance area product (RA) were achieved by inserting CoFe seed layer under the oxidized barrier. The MTJ satisfied over 10 16 write cycles at 10 ns pulse under the operation voltage of 0.65 V. From these results, we have verified for the first time the hypothesis that a spin transfer torque magnetoresistance random access memory (STT-MRAM) is suitable for a non-volatile working memory. © 2012 IEEE.


Banno N.,Low power Electronics Association and Project LEAP | Tada M.,Low power Electronics Association and Project LEAP | Sakamoto T.,Low power Electronics Association and Project LEAP | Okamoto K.,Low power Electronics Association and Project LEAP | And 4 more authors.
Digest of Technical Papers - Symposium on VLSI Technology | Year: 2012

A 32x32-crossbar complementary-atom-switch (CAS) block has been successfully integrated in a 65nm-node CMOS platform without degrading CMOS properties. The CAS connecting to two Cu lines at each edge is composed of a dual layered electrolyte of TiO 2/polymer, which prevents Cu oxidation during the fabrication of the switch and Cu BEOL. The reduction of Cu-surface roughness and the electric field concentration at the edge of Cu electrode enable a high I on/I off ratio and a low programming voltages of 1.8V with distribution as low as σ=0.2V. © 2012 IEEE.


Tada M.,Low power Electronics Association and Project LEAP | Sakamoto T.,Low power Electronics Association and Project LEAP | Hada H.,Low power Electronics Association and Project LEAP
ECS Transactions | Year: 2013

Opportunities and challenges of atom switch featuring Cu nanometer-scale conducting bridge in the solid-electrolyte are discussed with comparing the other emerging memories. Atom switch having the high on/off conductance ratio is suitable to directly replace the conventional CMOS switch element, realizing the low-power, nonvolatile programmable logic. Reliability challenges of the atom switch are also discussed in the view point of the stabilization of the on- and off-states. © The Electrochemical Society.


Aoki M.,Low power Electronics Association and Project LEAP | Noshiro H.,Low power Electronics Association and Project LEAP | Tsunoda K.,Low power Electronics Association and Project LEAP | Iba Y.,Low power Electronics Association and Project LEAP | And 7 more authors.
Digest of Technical Papers - Symposium on VLSI Technology | Year: 2013

We fabricated a new scalable multi-level cell for spin transfer torque magnetoresistive random-access memory that consists of stacked perpendicular magnetic tunnel junctions (MTJs) with a diameter of 50nm using one step etching. The cell features series-connecting MTJs using perpendicular magnetic anisotropy at the CoFeB/MgO interface and a well controlled stray field from the pinned layers resulting in Hshift∼0. The cell demonstrated four-level operation with low-voltage switching (< 0.5 V). © 2013 JSAP.


Yamamoto Y.,Low power Electronics Association and Project LEAP | Makiyama H.,Low power Electronics Association and Project LEAP | Shinohara H.,Low power Electronics Association and Project LEAP | Iwamatsu T.,Low power Electronics Association and Project LEAP | And 6 more authors.
IEEE Symposium on VLSI Circuits, Digest of Technical Papers | Year: 2013

We demonstrated record 0.37V minimum operation voltage (Vmin) of 2Mb Silicon-on-Thin-Buried-oxide (SOTB) 6T-SRAM. Thanks to the small variability of SOTB (AVT∼1.3 mVμm) and adaptive back biasing (ABB), Vmin was lowered down to ∼0.4 V regardless of temperature. Both fast access time and small standby leakage were achieved by ABB. © 2013 JSAP.


Takaura N.,Low power Electronics Association and Project LEAP
2014 IEEE International Nanoelectronics Conference, INEC 2014 | Year: 2014

The process and device technologies of topological-switching RAM (TRAM) were investigated. The sputtering and dry etching of GeTe/Sb2Te3 superlattice were developed as 300-mm-wafer processes. Fabrication and analyses of one-resistor and one-transistor one-resistor micro test structures revealed the electrical properties that were different from conventional phase change memory (PRAM). © 2014 IEEE.

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