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Sugii N.,Low Power Electronics Association and Project LEAP
Proceedings - IEEE International SOI Conference | Year: 2011

• Ultralow-power CMOS should be operated under E min condition in principle. • Compromise between E and speed is done with adaptive V dd and V b control. • Reducing RDF variability and back-bias control is a key requirement for ULV-operation CMOS. SOTB is the suitable device structure for this purpose. • From ULP application viewpoint, ULP wireless communication and power source are crucial issues as well as ULV LSIs. • "Perpetuum Mobile" microcomputer awaits vast new application field. © 2011 IEEE.

Sugii N.,Low Power Electronics Association and Project LEAP
Microelectronic Engineering | Year: 2015

Scaling the CMOS device has continuously improved its functionality and performance while lowering its power consumption and price. However, the current "scaled CMOS" technology faces several problems regarding power consumption, and a migration to new transistor structures is proceeding. "Fully depleted silicon on insulator" (FDSOI) technology can lower power consumption and improve performance of CMOS circuits with a capability of low-voltage operation. This article reviews advances in FDSOI technology: device structure, back-bias control function, fabrication process, demonstration of small variability of transistors, reliability including soft error, low voltage circuit design and silicon verification, and improvement in the energy efficiency of CMOS logic circuits. The strong requirement of further improvement in energy in the near future is finally pointed out. © 2014 Elsevier B.V. All rights reserved.

Ito K.,Keio University | Ogata T.,Keio University | Sakai T.,Low Power Electronics Association and Project LEAP | Awano Y.,Keio University
Applied Physics Express | Year: 2015

The structure dependence and electrical properties of a metal contact with multilayered graphene (MLG) have been investigated. We demonstrate the superiority of end- (or edge-) contact configurations for future three-dimensional (3D) interconnect applications. The contact resistivity of titanium end contacts can be lowered to 7.7 × 10-8 Ω cm2 by thermal annealing at 450 ° C, which is 2 orders of magnitude lower than that of conventional top-contact configurations, and to the best of our knowledge, it is the lowest value ever reported for a pristine MLG. X-ray photoelectron spectroscopy (XPS) measurements revealed the formation of covalent-bonded titanium carbide as an interface layer between the metal layer and MLG. © 2015 The Japan Society of Applied Physics

Takaura N.,Low Power Electronics Association and Project LEAP
2014 IEEE International Nanoelectronics Conference, INEC 2014 | Year: 2014

The process and device technologies of topological-switching RAM (TRAM) were investigated. The sputtering and dry etching of GeTe/Sb2Te3 superlattice were developed as 300-mm-wafer processes. Fabrication and analyses of one-resistor and one-transistor one-resistor micro test structures revealed the electrical properties that were different from conventional phase change memory (PRAM). © 2014 IEEE.

Masuhara T.,Low Power Electronics Association and Project LEAP
2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011 | Year: 2011

Future society requires networking of efficient portable, wearable, implantable IT/electronics and sensors for mobile, healthcare, smart grid and robot services. Power of small terminals operated by batteries or energy harvesting means, obviously need to be reduced. Power of data centers with much more processing capability and storage capacity compared to those now, also need to be reduced. Challenge toward low-voltage and low-power direction is, therefore, becoming increasingly important in future integrated circuits. © 2011 IEEE.

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