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Loongson Technology Corporation Ltd and CAS Institute of Computing Technology | Date: 2008-10-14

Calculating machines, namely, calculators, adding machines; data processors; computers; laptop computers; microprocessors; recorded computer software for computer system and/or application development, deployment and management; information processors, namely, central processing units; blank smart cards; notebook computers; computer memories; computer peripheral devices; Geiger counters; network communication apparatus, namely, computer network adapter, hubs, switches and routers; amusement apparatus, namely, video game machines adapted for use with television receivers only; integrated circuits; computer terminals; mechanisms for computer-operated apparatus, namely, computer cables, computer buffers, computer application software for mobile phones.


Trademark
Loongson Technology Corporation Ltd and CAS Institute of Computing Technology | Date: 2007-09-25

Calculating machines, namely calculators, adding machines; accounting machines, namely calculators, adding machines; data processing apparatus; computers; laptop computers; computer software for computer system and application development, deployment and management; microprocessors; information processors in the nature of central processing units; blank smart cards in the nature of integrated circuit cards; notebook computers.


Fu J.,University of Chinese Academy of Sciences | Fu J.,CAS Institute of Computing Technology | Jin G.,Loongson Technology Corporation Ltd | Zhang L.,CAS Institute of Computing Technology | Wang J.,CAS Institute of Computing Technology
2016 ACM International Conference on Computing Frontiers - Proceedings | Year: 2016

Dynamic compilation has a great impact on the performance of virtual machines. In this paper, we study the features of dynamic compilation and then unveil objectives for optimizing dynamic compilation systems. Following these objectives, we propose a novel dynamic compilation scheduling algorithm called combined analysis with online sifting (CAOS). It consists of a combined priority analysis model and an online sifting mechanism. The combined priority analysis model is used to determine the priority of methods while scheduling, aiming at reconciling responsiveness with the average delay of compilation queue. By performing online sifting, runtime overhead can be further reduced since methods with little benefit to performance are sifted out. CAOS can significantly improve the startup performance of applications. Experimental results show that CAOS achieves 14.0% improvement of startup performance on average, and the highest performance boost is up to 55.1%. With the virtue of high versatility and easy implementation, CAOS can be applied to most dynamic compilation systems. Source


Fu J.,University of Chinese Academy of Sciences | Fu J.,CAS Institute of Computing Technology | Jin G.,Loongson Technology Corporation Ltd | Zhang L.,CAS Institute of Computing Technology | Wang J.,CAS Institute of Computing Technology
Gaojishu Tongxin/Chinese High Technology Letters | Year: 2016

To reduce the overhead caused by instruction dispatch to improve the performance of interpreters, an instruction dispatch approach based on hardware and software co-design is proposed. Its main idea is to eliminate the expensive operation of constant address loading by optimizing the instruction dispatch table in the aspect of sofware, and to acceleratethe speed of memory access under the support of hardware by enhancing the processor's instruction set in the aspect of hardware. The hardware-software co-design can minimize the runtime overhead of instruction dispatch, thus improving the performance of interpreters. The experimental results showed that the proposed approach significantly improved the performance of interpreters. For benchmarks of SPECjvm98 and DaCapo, the overall performance of interpreters was improved by 11.5%, and the highest performance boost was up to 15.4%. The approach is highly versatile, easy to implement and can be applied to the design and implementation of high performance interpreters on mainstream processors. © 2016, Inst. of Scientific and Technical Information of China. All right reserved. Source


Zhu X.-J.,Chinese Academy of Sciences | Zhu X.-J.,Loongson Technology Corporation Ltd
Jisuanji Xuebao/Chinese Journal of Computers | Year: 2011

The development of integrated circuits makes the number of on-chip cores increase. Communication among the cores demands higher throughput, lower latency and more scalability. Traditional on-chip bus can not satisfy the need of on-chip communication. So researchers present a new interconnect architecture, called network on chip. In order to meet the special demand of network on chip, this paper gives a scalable topology named Rgrid and its routing algorithm called DR. Rgrid can reduce the average hops between on-chip cores, whose physical implementation is much easier than Torus topology. The author implements the Rgrid and Mesh tolopogies in the Godson3 simulator. The simulation results show that, simulator can gain much better performance using Rgrid topology than using Mesh topology for the Splash2 benchmarks. Compared to Mesh topology, the IPC of benchmarks of Rgrid increases by 0.5%~148%, the average latency degrades by 5%~81%. Source

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