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Alhussien H.,Link A Media Devices | Moon J.,KAIST
IEEE Journal on Selected Areas in Communications | Year: 2010

The error pattern correcting code (EPCC) can be constructed to provide a syndrome decoding table targeting the dominant error events of an inter-symbol interference channel at the output of the Viterbi detector. For the size of the syndrome table to be manageable and the list of possible error events to be reasonable in size, the codeword length of EPCC needs to be short enough. However, the rate of such a short length code will be too low for hard drive applications. To accommodate the required large redundancy, it is possible to record only a highly compressed function of the parity bits of EPCC's tensor product with a symbol correcting code. In this paper, we show that the proposed tensor error-pattern correcting code (T-EPCC) is linear time encodable and also devise a low-complexity soft iterative decoding algorithm for EPCC's tensor product with q-ary LDPC (T-EPCC-qLDPC). Simulation results show that T-EPCC-qLDPC achieves almost similar performance to single-level qLDPC with a 1/2 KB sector at 50% reduction in decoding complexity. Moreover, 1 KB T-EPCC-qLDPC surpasses the performance of 1/2 KB single-level qLDPC at the same decoder complexity. © 2010 IEEE.

Tang X.,Link A Media Devices | Wang S.,NEC Laboratories
IEEE Transactions on Computers | Year: 2010

A self-diagnosis circuit that can be used for built-in self-repair is proposed. The circuit under diagnosis is assumed to be composed of a large number of field repairable units (FRUs), which can be replaced with spares when they are found to be defective. Since the proposed self-diagnosis circuit is implemented on the chip, responses that are scanned out of scan chains are compressed by the group compactor, the space compression circuit, and finally, the time compression circuit to reduce the volume of test response data. Both the space and time compression circuits implement a Reed-Solomon code. Unlike prior work, in the proposed technique, responses of all FRUs are observed at the same time to reduce diagnosis time. The proposed diagnosis circuit can locate up to l defective FRUs. We propose a novel space compression circuit that reduces hardware overhead by exploiting the frequency difference of the scan shift clock and the system clock and by combining scan cells into groups of size r. When the size of constituent multiple-input signature register (MISR) is m, the total number of signatures to be stored for the fault-free signature is 2lmB bits, where 1\le B \le m. The experimental results show that the proposed diagnosis circuit that can locate up to four defective FRUs in the same test session can be implemented with less than one percent of hardware overhead for a large industrial design. Hardware overhead for the diagnosis circuit is lower for large CUDs. © 2006 IEEE.

Zhang X.,Case Western Reserve University | Wu Y.,Link A Media Devices | Zhu J.,Case Western Reserve University
Proceedings - IEEE International Symposium on Circuits and Systems | Year: 2011

Algebraic soft-decision decoding (ASD) of Reed-Solomon (RS) codes can achieve substantial coding gain with polynomial complexity. Particularly, the low-complexity Chase (LCC) ASD decoding has better performance-complexity tradeoff. In the LCC decoding, 2ν test vectors need to be interpolated over, and a polynomial selection scheme needs to be employed to select one interpolation output to send to the rest decoding steps. The polynomial selection can account for a significant proportion of the overall LCC decoder area, especially in the case of long RS codes and large ν. In this paper, a novel low-complexity polynomial selection scheme is proposed and efficiently incorporated into the LCC decoder. By sacrificing one single message symbol and modifying the encoder slightly, the polynomial selection is done using simple computations. For a (458, 410) RS code over GF(210), the encoder and LCC decoder with ν= 8 employing the proposed scheme requires 34% less area without changing the encoding or decoding throughput. © 2011 IEEE.

Bellorado J.,Link A Media Devices | Kavcic A.,University of Hawaii at Manoa | Marrow M.,Link A Media Devices | Ping L.,City University of Hong Kong
IEEE Transactions on Information Theory | Year: 2010

In this paper, we present a practical approach to the iterative decoding of Reed-Solomon (RS) codes. The presented methodology utilizes an architecture in which the output produced by steps of belief-propagation (BP) is successively applied to a legacy decoding algorithm. Due to the suboptimal performance of BP conducted on the inherently dense RS parity-check matrix, a method is first provided for the construction of reduced-density, binary, parity-check equations. Iterative decoding is then conducted utilizing a subset of a redundant set of parity-check equations to minimize the number of connections into the least-reliable bits. Simulation results show that performance comparable to (and exceeding) the best known practical RS decoding techniques is achievable with the presented methodology. The complexity of the proposed algorithm is significantly lower than these existing procedures and permits a practical implementation in hardware. © 2006 IEEE.

Bellorado J.,Link A Media Devices | Kavcic A.,University of Hawaii at Manoa
IEEE Transactions on Information Theory | Year: 2010

In this paper, we present an algebraic methodology for implementing low-complexity, Chase-type, decoding of Reed-Solomon (RS) codes of length n. In such, a set of 2ηtest-vectors that are equivalent on all except η ≪ n coordinate positions is first produced. The similarity of the test-vectors is utilized to reduce the complexity of interpolation, the process of constructing a set of polynomials that obey constraints imposed by each test-vector. By first considering the equivalent indices, a polynomial common to all test-vectors is constructed. The required set of polynomials is then produced by interpolating the final η dissimilar indices utilizing a binary-tree structure. In the second decoding step (factorization) a candidate message is extracted from each interpolation polynomial such that one may be chosen as the decoded message. Although an expression for the direct evaluation of each candidate message is provided, carrying out this computation for each polynomial is extremely complex. Thus, a novel, reduced-complexity, methodology is also given. Although suboptimal, simulation results affirm that the loss in performance incurred by this procedure is decreasing with increasing code length n, and negligible for long $(n > 100)$ codes. Significant coding gains are shown to be achievable over traditional hard-in hard-out decoding procedures (e.g., Berlekamp-Massey) at an equivalent (and, in some cases, lower) computational complexity. Furthermore, these gains are shown to be similar to the recently proposed soft-in-hard-out algebraic techniques (e.g., Sudan, Kötter-Vardy) that bear significantly more complex implementations than the proposed algorithm. © 2006 IEEE.

Zhang X.,Case Western Reserve University | Zheng Y.,Case Western Reserve University | Wu Y.,Link A Media Devices
2012 International Conference on Computing, Networking and Communications, ICNC'12 | Year: 2012

With polynomial complexity, algebraic soft-decision (ASD) decoding of Reed-Solomon (RS) codes can achieve significant coding gain over hard-decision decoding. Compared to other existing ASD algorithms, the low-complexity Chase (LCC) decoding that tests 2η vectors has lower hardware complexity since the multiplicities of the involved interpolation points are all one. However, its complexity increases significantly with η. On the other hand, magnetic recording uses long RS codes, and hence larger η needs to be adopted to achieve good performance. This paper proposes a novel scheme to integrate the Kötter-Vardy (KV) scheme into the Chase decoding. To reduce the hardware complexity, the maximum multiplicity is limited to two. Nevertheless, the proposed KV-LCC scheme can achieve similar performance as the LCC algorithm by using a much smaller η. In addition, a simplified (S-) version of the KV-LCC scheme is developed without losing coding gain. To achieve similar performance as the LCC algorithm, the S-KV-LCC decoding requires 63% less multiplications for a (458, 410) RS code over GF(210). © 2012 IEEE.

Fojtik M.,University of Michigan | Kim D.,Intel Corporation | Chen G.,Intel Corporation | Lin Y.-S.,IBM | And 7 more authors.
IEEE Journal of Solid-State Circuits | Year: 2013

An 8.75 mm3 microsystem targeting temperature sensing achieves zero-net-energy operation using energy harvesting and ultra-low-power circuit techniques. A 200 nW sensor measures temperature with-1.6°C/+3°C accuracy at a rate of 10 samples/sec. A 28 pJ/cycle, 0.4 V, 72 kHz ARM Cortex-M3 microcontroller processes temperature data using a 3.3 fW leakage per bit SRAM. Two 1 mm2 solar cells and a thin-film Li battery power the microsystem through an integrated power management unit. The complete microsystem consumes 7.7 μ W when active and enters a 550 pW data-retentive standby mode between temperature measurements. The microsystem can process temperature data hourly for 5 years using only the initial energy stored in the battery. This lifetime is extended indefinitely using energy harvesting to recharge the battery, enabling energy-autonomous operation. © 1966-2012 IEEE.

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