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Ravel L.,STMicroelectronics | Brault C.,Dow Advanced Materials | Hegaret C.,Lfoundry | Di Giacomo A.,STMicroelectronics | And 3 more authors.
Proceedings of SPIE - The International Society for Optical Engineering | Year: 2011

The thickness for a material to be used for photolithography process is typically monitored on test wafers with a completely flat surface. Therefore material's specification is limited to thickness uniformity, reflectance, refractive indexes and chemical properties. NVM embedded IC's integrating a variety of devices within the same chip may lead to challenging topography at gate level. Tight control of transistors CD, coherent with model based OPC treatments precision, is hard to achieve in circuitry regions with small surface before resist coating. The proposed model is based on reflectance increase in areas where observed CD is small with respect to the target. The observed root cause of CD loss is linked with materials' behavior in the proximity of edges of silicon structures and with the overall thickness reduction when the blocks become small. A set of test patterns is defined and substrates are prepared with planarizing and conformal BARC's to quantify the influence of topography on the CD. The geometries provide a good sampling in terms surface. After lithography, the dimensional effects are quantified by top view SEM. A model describing materials thinning can be computed from CD behavior data in the case of inorganic BARC. The study shows the limitations of both types of BARC's and suggests that Optical Proximity Correction could be used to compensate the effects of topography. Some recommendations are made in order to fulfill 65nm and smaller technology nodes' requirements. Several components of the study can be combined to master topography effects in complex process flows. © 2011 SPIE. Source

Yugma C.,Ecole Nationale Superieure des Mines de Saint - Etienne CMP | Dauzere-Peres S.,Ecole Nationale Superieure des Mines de Saint - Etienne CMP | Rouveyrol J.-L.,Ecole Nationale Superieure des Mines de Saint - Etienne CMP | Vialletelle P.,STMicroelectronics | And 2 more authors.
Proceedings - Winter Simulation Conference | Year: 2011

As modern manufacturing technology progresses, measurement tools become scarce resources since more and longer control operations are required. It thus becomes critical to decide whether a lot should be measured or not in order to get as much information as possible on production tools or processes, and to avoid ineffective measurements. To minimize risks and optimize measurement capacity, a smart sampling algorithm has been proposed to efficiently select and schedule production lots on metrology tools. This algorithm and others have been embedded in a simulator called "Smart Sampling Scheduling and Skipping Simulator" (S5). The characteristics of the simulator will be presented. Simulations performed on several sets of instances from three different semiconductor manufacturing facilities (or fabs) will be presented and discussed. The results show that, by using smart sampling, it is possible to drastically improve various factory performance indicators when compared to current fab sampling. © 2011 IEEE. Source

Organtini P.,Micron Technology Inc. | Russo F.,Lfoundry
IEEE Transactions on Semiconductor Manufacturing | Year: 2013

This paper presents a novel approach to modeling yield using the Gompertz function, which is widely used in biology to model the growth processes of plants, tumors, etc. We demonstrate that the yield-learning process in a semiconductor fab follows the same behavior of the growth of biological systems. We start with a simple time series model, which describes the learning process in terms of defect density reduction. Then we obtain the Gompertz growth model, which also fits the experimental data better than more traditional learning models such as the Gruber' s general yield learning model . © 1988-2012 IEEE. Source

Forli L.,Lfoundry | Picart B.,Lfoundry | Reverdy A.,Sector Technologies | Schlangen R.,DCG Systems
Conference Proceedings from the International Symposium for Testing and Failure Analysis | Year: 2011

In this paper, we demonstrate that lock-in thermography (LIT) appears as a key and complementary technique for Failure Analysis across different use cases. Even if the failure requires a complex emulation setup, thanks to a specific capability of our thermal system, this kind of failure can be addressed. In our FA case study, we will show that LIT is a most efficient solution to address a bridge defect located inside a complex logic area, and furthermore that LIT highlights the defect itself and not only the consequences of the defect. Copyright © 2011 ASM International®. All rights reserved. Source

Polignano M.L.,STMicroelectronics | Codegoni D.,STMicroelectronics | Galbiati A.,STMicroelectronics | Grasso S.,STMicroelectronics | And 4 more authors.
ECS Journal of Solid State Science and Technology | Year: 2016

Various measurement techniques are compared and the most suitable methods for contamination detection are identified. The results of this study show that it is not possible to define a unique recipe that can be applied in all cases. Concerning metal contaminants, the stratigraphic in-depth distribution and hence the diffusivity of contaminants determines the most effective approach. Iron and palladium are chosen as the examples of fast diffusers, molybdenum and tungsten as slow diffusers. Fast diffusers like iron and palladium diffuse through several hundred microns during an ordinary thermal treatment. Minority carrier lifetime measurements are probably the best choice to detect these contaminants. Molybdenum and tungsten do not diffuse deep enough to be efficiently revealed by recombination lifetime measurements, but are easily revealed in the silicon volume by DLTS. Because of their low diffusivity, a very small amount of these elements per unit surface may result in a significant concentration in the near-surface region where devices are built. Ion implantation is confirmed to be an important source of metal contamination. It is shown that ion implantation can be responsible both for iron contamination and for contamination by slow diffusers, such as molybdenum and tungsten. A procedure for monitoring molybdenum and tungsten contamination in ion implantation processes by DLTS is defined and calibrated. Finally, the efficiency of some gettering techniques in reducing iron, molybdenum and tungsten contamination is discussed. Gettering is found to be active at relatively high contaminant concentrations, but low contamination levels are not gettered under our experimental conditions. Carbon implantation showed partial efficiency in gettering molybdenum and tungsten, whereas gettering did not take place after silicon implantation. © 2015 The Electrochemical Society. Source

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