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Prasad J.S.,LBRCE | Obulesh Y.P.,Koneru Lakshmaiah College of Engineering | Babu C.S.,JNTUK Kakinda
Journal of Electrical Systems | Year: 2017

The use of conventional dc-dc converter is likely to decrease the efficiency because of the hard switching, which generates switching losses during switching on/off states. The proposed converter has the following desirable features: It requires only five control switches out of which four main control switches operate under zero voltage switching and one auxiliary control switch which operates under zero current switching; Three level voltage waveform before output filter can be achieved, which significantly reduces the value of filter inductance as compared to the existing topologies; Soft switching occurs at small value of leakage inductance of high frequency transformer; Modified phase shift pulse width modulated control method is used to achieve wide output range. Hence, the cost and switching losses are reduced to a greater extent, thus improves the overall efficiency of a system. This paper describes the main operational modes and design equations of the proposed converter. The simulation and experimental results are presented to validate the feasibility of proposed work. © JES 2017.

Nireekshana T.,VNRVJIET | Rao G.K.,LBRCE | Raju S.S.N.,Jawaharlal Nehru Technological University Kakinada
ICECT 2011 - 2011 3rd International Conference on Electronics Computer Technology | Year: 2011

Since a couple of decades ago voltage stability assessment has received an increasing attention due to complexity of the power system. With the increase in power demand and limited power sources has caused the system to operate at its maximum capacity. It demonstrates line stability index in order to determine voltage stability limits in the power system. Promoting open access in the electricity industry has ultimately forced power systems around the globe to run closer to their operating limits. Many past experiences and recent incidents have once again highlighted the significance of power system security issues, and costs of its negligence can prove to be catastrophic. In this paper the line stability indices and the feasibility limit at different cases of line outages and generator outages are calculated. A case study of a 9-bus system and IEEE 30-bus Systems are presented to demonstrate the proposed technique. © 2011 IEEE.

Subba Rao N.V.,LBRCE | Kesava Rao G.,VVIT | Sivanagaraju S.,J.N.T.U.K
2012 International Conference on Advances in Power Conversion and Energy Technologies, APCET 2012 | Year: 2012

This paper proposes an efficient solution to the problem of power flow tracing in electrical transmission networks. In a competitive-market environment, deregulation of the electricity industry and thus transmission open access make it even more important to allocate the cost of transmission service fairly. Graph method and the proportional-sharing principle are employed to trace power flow; the results are then employed to determine the real power contribution of generators to lines and loads. The sequence of tracing of nodes is determined by using Breadth First Search technique. The proposed method can also be applied for reactive power tracing. The algorithm is tested on a 6 bus system. © 2012 IEEE.

Rao A.P.C.,PVPSIT | Obulesh Y.P.,LBRCE | Babu C.S.,JNTUK
ARPN Journal of Engineering and Applied Sciences | Year: 2012

In the recent past, variable speed driving systems have sprouted in various small scale and large scale applications like automobile industries, domestic appliances etc. The usage of green and eco friendly electronics are greatly developed to save the energy consumption of various devices. This lead to the development in Brushless DC motor (BLDCM). The usage of BLDCM enhances various performance factors ranging from higher efficiency, higher torque in low-speed range, high power density, low maintenance and less noise than other motors. The BLDCM can act as an alternative for traditional motors like induction and switched reluctance motors. In this paper we present a mathematical model of BLDC motor and show the values of various technical parameters using MATLAB/SIMULINK. In this paper the simulation is carried out for 120 degree mode of operation. The test results show the performance of BLDCM which are highly acceptable. Finally a PID controller is applied for closed loop speed control under various loading conditions. © 2006-2012 Asian Research Publishing Network (ARPN).

Nireekshana T.,VNRVJIET | Rao G.K.,LBRCE | Raju S.S.N.,Jawaharlal Nehru Technological University Anantapur
ICECT 2011 - 2011 3rd International Conference on Electronics Computer Technology | Year: 2011

Flexible Alternating Current Transmission Systems (FACTS) devices have been proposed to be effective for controlling power flow and regulating bus voltage in electrical power systems, resulting in an increased transfer capability, low system losses and improved stability. Unified Power Flow Controller (UPFC) is one of the most promising FACTS devices for power flow control. In principle, the UPFC is capable of providing active and reactive power control, as well as adaptive voltage magnitude control. Provided no operating limits are violated, the UPFC regulates all three variables simultaneously or any combination of them. Moreover, since the UPFC parameters are computed after the load flow has converged, there is no way of knowing during the iterative process whether or not the UPFC parameters are within limits. This has provided the motivation for developing a new UPFC model suitable for incorporating into an existing Newton-Raphson load flow algorithm. It is also necessary to determine the optimal setting of the device so that the net saving is maximized. In this work a new mathematical model of UPFC is developed which can be easily incorporated in Newton-Raphson load flow algorithm. Optimal location of UPFC is determined based on Voltage Stability Index. Particle Swarm Optimization (PSO) technique is used to set the parameters UPFC. The objective function formulated consists of two terms: cost for energy loss and cost related to UPFC, which has to be maximized for net saving. The results obtained using PSO is compared with that of results obtained using genetic algorithm. The validity of the proposed work is tested on IEEE 5-Bus and IEEE 14-Bus systems using MATLAB. © 2011 IEEE.

Murthy G.L.N.,LBRCE | Anuradha B.,SVUCE | Pullarao C.,LBRCE
International Journal of Applied Engineering Research | Year: 2014

Effective diagnosis and treatment planning of disease using Magnetic Resonance (MR) images heavily lies on the accuracy of noise removal. MR images are often distorted by different types of noise which in turn affects various sub processes involved including feature extraction. In this paper, an attempt is made to design such an algorithm capable of handling various types of noise. While conventional filtering algorithms in spatial domain operate directly on the pixel values, the proposed algorithm will be based on depth between pixels. The filtering process is carried out by assigning positive quantities in the neighborhood of corrupted pixels. Root Mean Square Error (RMSE) is used as the quantifying measure of the proposed algorithm. The qualitative and quantitative results shows that the proposed algorithm suits best for achieving required noise cancellation. © 2014, Research India Publications.

Reddy S.S.S.,LBRCE | Suresh G.V.,LBRCE | Reddy T.R.,SIET | Vardhan B.V.,JNTUCEJ
Advances in Intelligent Systems and Computing | Year: 2013

Data uncertainty due to various causes, including imprecise measurement, network latency, out-dated sources and sampling errors, is common in real-world applications. Data Analysis applications are typical in collecting and accumulating large amounts of uncertain data. This attracted more and more database community to analyze and resolve the uncertainty incured in the large data sets. We, in this article, present a naive classifier, which is a Set-Valued counterpart of Naive Bayes that is extended to a general and flexible treatment of incomplete data, yielding to a new classifier called Naïve Credal Classifier. Naïve Credal Classifieris an application on closed and convex sets of probability distributions called Credal sets, of uncertainty measures. The Naïve Credal Classifier extends the discrete Naive Bayes classifier to imprecise probabilities and also models both prior ignorance and ignorance about the likelihood by sets of probability distributions. This is a new means to deal with uncertain data sets that departs significantly from most established conventional classification methods. Experimental results show that proposed model exhibits reasonable accuracy performance in classification on uncertain data. © 2013 Springer-Verlag.

Reddy B.N.K.,Koneru Lakshmaiah College of Engineering | Suresh N.,Koneru Lakshmaiah College of Engineering | Ramesh J.V.N.,Koneru Lakshmaiah College of Engineering | Pavithra T.,Koneru Lakshmaiah College of Engineering | And 3 more authors.
2015 International Conference on Advances in Computing, Communications and Informatics, ICACCI 2015 | Year: 2015

Programming of Field Programmable Gate Arrays (FPGAs) have long been the domain of engineers with VHDL or Verilog expertise. FPGA's have caught the attention of algorithm developers and communication researchers, who want to use FPGAs to instantiate systems or implement DSP algorithms. These efforts however, are often stilled by the complexities of programming FPGAs. RTL programming in either VHDL or Verilog is generally not a high level of abstraction needed to represent the world of signal How graphs and complex signal processing algorithms. This paper describes the FPGA Programs using Graphical Language rather than Verilog VHDL with the help of LabVIEW and features of the LabVIEW FPGA environment. © 2015 IEEE.

Jayasree K.,L.B.R.C.E | Reddy B.N.K.,NIT Goa | Kumar B.S.,P.A. College | Ramesh J.V.N.,Koneru Lakshmaiah College of Engineering | And 2 more authors.
ACM International Conference Proceeding Series | Year: 2015

Multiprocessor system-on-chip (MPSoC) architectures have risen as a prevalent answer to the ever-increasing performance & reduce the power consumption requirements, that are customized to a specific application have the potential to achieve very high performance, while additionally obliging low power consumption. The power consumed and performance of the system mainly depend on the memory and communication medium of processors. There are some issues involved in memory and communication of processors. In this paper we try to avoid those issues and show two separate techniques to increase performance and reduce the power consumption. The first technique is Scratch Pad Memory (SPM) Replacement rather than cache replacement, second technique is Network on Chip (NOC) rather than Advanced Microcontroller Bus Architecture (AMBA) communication medium between processors. © 2015 ACM.

Uma Vani M.,L.B.R.C.E. | Ramana Rao P.V.,National Institute of Technology Warangal
Proceedings - 2010 International Conference on Computational Intelligence and Communication Networks, CICN 2010 | Year: 2010

This paper discusses the impact of HVDC on Power System Stability and proposes a new type of control mechanism based on Fuzzy set theory to augment dynamic performance of a multi-machine power system. To have good damping characteristics over a wide range of operating conditions, speed deviation (Δω = error1) and acceleration (Δ ώ = error3 ), of the machines are chosen as the input signals to the fuzzy controller. These input signals are first characterized by a set of linguistic variables using fuzzy set notations.The fuzzy relation matrix allows a set of fuzzy logic operations that are performed on controller inputs to obtain the desired output. The effectiveness of the proposed controller is demonstrated by a multi-machine system example. The superior performance of this fuzzy controller in comparison to the conventional fixed gain controller proves the efficiency of this new fuzzy PID controller. © 2010 IEEE.

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