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Hillsboro, OR, United States

Lattice Semiconductor Corporation is a United States based manufacturer of high-performance programmable logic devices . Founded in 1983, the company employs about 700 people and has annual revenues of around $300 million, with Darin Billerbeck as the chief executive officer. The Oregon-based company is the number three ranked company in world market share for field programmable gate array devices, and number two for CPLDs & SPLDs. The company went public in 1989 and is traded on the NASDAQ stock exchange under the symbol LSCC. Wikipedia.

Lattice Semiconductor | Date: 2016-01-07

A first network signal is received indicating a device identifier in response to a transaction involving an electronic device uniquely associated with the device identifier. An entity identifier specific to an entity associated with the transaction is determined. In response to an initialization event of the electronic device, a second network signal from the electronic device is received that identifies the electronic device. In response to the second network signal, a configuration is communicated to the electronic device that is specific to the entity associated with the transaction.

In certain embodiment, built-in self-test (BIST) circuitry for multiport memory comprises a configurable address generator and a configurable data generator. The configurable address generator can be configured to concurrently generate first and second logical memory addresses corresponding to physically neighboring first and second memory cells of the multiport memory for any selected memory mode of a plurality of available memory modes having different column-multiplexing schemes. The configurable data generator can be configured to concurrently generate two sets of data for the selected memory mode, such that (i) the first set of data is written into and read from the multiport memory via a first memory port using the first logical memory address and (ii) the second set of data is written into and read from the multiport memory via a second memory port using the second logical memory address. The BIST circuitry enables efficient, physically aware built-in self-testing.

Lattice Semiconductor | Date: 2014-10-08

Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a programmable logic device (PLD). The computer-implemented method also includes synthesizing the design into a plurality of PLD components comprising a first logic block cascaded into a second logic block. In the computer-implemented method, the second logic block implements a multiplexer adapted to selectively pass a first multi-bit input signal received from the first logic block or a second multi-bit input signal. The computer-implemented method also includes further synthesizing the design to absorb the multiplexer into the first logic block.

Lattice Semiconductor | Date: 2015-10-19

One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell and to configure a volatile output based on the program state of the NVM cell. The NVM cell comprises a first anti-fuse device, a first select device connected in series with the first anti-fuse device at a first node, and a first pass device. The memory circuit also may have a programmable (independently of the NVM cell) volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell. The NVM cell may have two NV elements that are separately programmable and are separately selectable via separate access transistors to drive the VM input node.

Lattice Semiconductor | Date: 2015-01-30

Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and a plurality of logic cells within at least one of the PLBs, where each logic cell includes a four input lookup table (4-LUT) configured to provide a 4-LUT output signal to associated carry logic. Each logic cell is configurable according to at least two selectable operational modes including a logic function output mode and a ripple arithmetic output mode, and at least three of the 4-LUT inputs are interchangeable when a selected operational mode comprises the ripple arithmetic output mode.

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