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Goto T.,Tohoku University | Kuroda R.,Tohoku University | Akagawa N.,Tohoku University | Suwa T.,Tohoku University | And 8 more authors.
ECS Journal of Solid State Science and Technology | Year: 2016

Atomically flattening technology was introduced to the widely used complementary metal oxide silicon process employing sallow trench isolation at the 0.22-μm technology node. Two methods were investigated. The first method is to apply the atomically flattening to the starting Si wafer, and the second method is to apply this just before forming the gate oxide. In both methods, atomically flat gate insulator/Si interface could be obtained, and the test array circuit for evaluating the electrical characteristics of many (>130,000) metal oxide semiconductor field effect transistors was successfully fabricated on an entire 200-mm-diameter wafer. By evaluating the test circuit, the noise amplitude of the gate-source voltage related to the random telegraph noise was reduced owing to introducing the atomically flat gate insulator/Si interface. The charge-to-breakdown of the gate oxide was also improved. © 2015 The Electrochemical Society. All rights reserved.

Inatsuka T.,Tohoku University | Kumagai Y.,LAPIS Semiconductor Miyagi Co. | Kuroda R.,Tohoku University | Teramoto A.,Tohoku University | And 3 more authors.
IEEE Transactions on Semiconductor Manufacturing | Year: 2013

We discuss the measurement accuracy of the test circuit, which can evaluate statistical characteristics of gate leakage current of small area metal-oxide-semiconductor field-effect transistors (MOSFETs) in a very short time. The accuracy and precision of the gate leakage current obtained by the test circuit are verified for a wide range. As a result it is confirmed that very accurate gate current of 10-17 A±10\% is able to be measured with this method. Using this test circuit, we can evaluate the gate leakage current at a wide electric field range, which is important in discussing the conduction mechanism of gate leakage current. © 1988-2012 IEEE.

Goto T.,Tohoku University | Kuroda R.,Tohoku University | Akagawa N.,Tohoku University | Suwa T.,Tohoku University | And 9 more authors.
Japanese Journal of Applied Physics | Year: 2015

By introducing high-purity and low-temperature Ar annealing at 850 °C, atomically flat Si surfaces of silicon-on-insulator (SOI) and shallow-trenchisolation (STI)-patterned wafers were obtained. In the case of the STI-patterned wafer, this low-temperature annealing and subsequent radical oxidation to form a gate oxide film were introduced into the complementary metal oxide semiconductor (CMOS) process with 0.22μm technology. As a result, a test array circuit for evaluating the electrical characteristics of a very large number (>260,000) of metal oxide semiconductor field effect transistors (MOSFETs) having an atomically flat gate insulator/Si interface was successfully fabricated on a 200-mm-diameter wafer. By evaluating 262,144 nMOSFETs, it was found that not only the gate oxide reliability was improved, but also the noise amplitude of the gate-source voltage related to the random telegraph noise (RTN) was reduced owing to the introduction of the atomically flat gate insulator/Si interface. © 2015 The Japan Society of Applied Physics.

Goto T.,Tohoku University | Kuroda R.,Tohoku University | Suwa T.,Tohoku University | Teramoto A.,Tohoku University | And 7 more authors.
ECS Transactions | Year: 2015

Low temperature (800 °C-900 °C) Ar annealing for atomically flattening was applied to shallow trench isolation (STI)-patterned wafers where Si and SiO2 coexist on the wafer surface. During the Ar annealing, concentrations of H2O and O2 residual gases in the annealing ambience was maintained at low level less than 30 ppb. Such low temperature and clean Ar ambience can suppress oxidation and etching of Si surface as well as a decomposition of thick SiO2 film for device isolation. As a result, the atomically flat Si surface was obtained for the Si active pattern having STI edge by the Ar annealing at 800 °C-900 °C. Owing to the introduction of the atomically flat Si/gate oxide interface, breakdown characteristic of the fabricated MOS capacitors was improved for the atomically flat devices. © The Electrochemical Society.

Ida J.,Kanazawa Institute of Technology | Mori T.,Kanazawa Institute of Technology | Kuramoto Y.,Kanazawa Institute of Technology | Horii T.,Kanazawa Institute of Technology | And 5 more authors.
Technical Digest - International Electron Devices Meeting, IEDM | Year: 2016

We propose and demonstrate a super steep Subthreshold Slope (SS) new type SOI FET with a PN-body tied structure. It has a symmetry source and drain (S/D) structure. The device shows a super steep SS (<6mV/dec) over 3 decades of the drain current with an ultralow drain voltage down to 0.1V. It also shows a low leakage current (below 1pA/um), a good Id-Vd characteristic and a negligible hysteresis characteristic. © 2015 IEEE.

Futagawa M.,University of Shizuoka | Ito T.,University of Shizuoka | Kunii A.,LAPIS Semiconductor Miyagi Co. | Watanabe M.,LAPIS Semiconductor Co. | And 4 more authors.
2015 IEEE SENSORS - Proceedings | Year: 2015

To minimize the damage caused by slope failure, knowledge of the increase in water content in mountain soil is important. Our group has been studying miniaturized impedance sensor for multipoint measurements in the soil. To improve contact characteristics between sensor surface and free water in soil, SiOx film of hydrophilic property covered on our conventional sensor chip. For contact property test, the sensor chip measured impedance of model soils. The proposed sensor achieved to stable contact the free water in the soil. Moreover, the chip operated for long period of time in mountain slope. The sensor could measure nearly theoretical outputs which responded to rainfalls. We succeeded to fabricate the stably soil monitor sensor with hydrophilic film SiOx. © 2015 IEEE.

Watanabe M.,LAPIS Semiconductor Co. | Nakamura A.,LAPIS Semiconductor Co. | Kunii A.,LAPIS Semiconductor MIYAGI Co. | Kusano K.,LAPIS Semiconductor MIYAGI Co. | Futagawa M.,University of Shizuoka
Journal of Physics: Conference Series | Year: 2015

A scalable indoor light energy harvester was fabricated by microelectromechanical system (MEMS) and printing hybrid technology and evaluated for agricultural IoT applications under different environmental input power density conditions, such as outdoor farming under the sun, greenhouse farming under scattered lighting, and a plant factory under LEDs. We fabricated and evaluated a dye- sensitized-type solar cell (DSC) as a low cost and "scalable" optical harvester device. We developed a transparent conductive oxide (TCO)-less process with a honeycomb metal mesh substrate fabricated by MEMS technology. In terms of the electrical and optical properties, we achieved scalable harvester output power by cell area sizing. Second, we evaluated the dependence of the input power scalable characteristics on the input light intensity, spectrum distribution, and light inlet direction angle, because harvested environmental input power is unstable. The TiO2 fabrication relied on nanoimprint technology, which was designed for optical optimization and fabrication, and we confirmed that the harvesters are robust to a variety of environments. Finally, we studied optical energy harvesting applications for agricultural IoT systems. These scalable indoor light harvesters could be used in many applications and situations in smart agriculture. © Published under licence by IOP Publishing Ltd.

Honda S.,University of Tsukuba | Hara K.,University of Tsukuba | Asano M.,University of Tsukuba | Maeda T.,University of Tsukuba | And 9 more authors.
IEEE Nuclear Science Symposium Conference Record | Year: 2013

We are developing monolithic pixel sensors based on a 0.2 μm fully-depleted silicon-on-Insulator (SOI) technology. The major issue in applications them in high-radiation environments is the total ionization damage (TID) effects. The effects are rather substantial in the SOI devices since the transistors are enclosed in the oxide layers where generated holes are trapped and affect the operation of the near-by transistors. The double SOI sensors that provide an independent electrode underneath the buried oxide layer have been developed. We have irradiated transistor test elements and pixel sensors with γ-rays. By adjusting the potential of this electrode, the TID effects are shown to be compensated. The pixel sensor irradiated to 20 kGy recovered its functionality by applying a bias to the electrode. The radiation tolerance of the SOI devices has been substantially improved by the double SOI. © 2013 IEEE.

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