Fremont, CA, United States
Fremont, CA, United States

Lam Research Corporation is an American corporation that engages in the design, manufacture, marketing, and service of semiconductor processing equipment used in the fabrication of integrated circuits. Its products include etch systems, including dielectric and conductor etch, chemical vapor deposition , plasma-enhanced chemical vapor deposition , physical vapor deposition , electrochemical deposition , ultraviolet thermal processing , and resist strip and surface preparation, as well as synergy cleaning products. The company markets its products and services primarily to companies involved in the production of semiconductors in the United States, Europe, Asia Pacific, Korea, and Japan. Lam Research Corporation was founded in 1980 by Dr. David K. Lam and is headquartered in Fremont, California. Wikipedia.

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A wafer is positioned on a wafer support apparatus beneath an electrode such that a plasma generation region exists between the wafer and the electrode. Radiofrequency power is supplied to the electrode to generate a plasma within the plasma generation region during multiple sequential plasma processing cycles of a plasma processing operation. At least one electrical sensor connected to the electrode measures a radiofrequency parameter on the electrode during each of the multiple sequential plasma processing cycles. A value of the radiofrequency parameter as measured on the electrode is determined for each of the multiple sequential plasma processing cycles. A determination is made as to whether or not any indicatory trend or change exists in the values of the radiofrequency parameter as measured on the electrode over the multiple sequential plasma processing cycles, where the indicatory trend or change indicates formation of a plasma instability during the plasma processing operation.


A wafer is positioned on a wafer support apparatus beneath an electrode such that a plasma generation region exists between the wafer and the electrode. Radiofrequency power is supplied to the electrode to generate a plasma within the plasma generation region. Optical emissions are collected from the plasma using one or more optical emission collection devices, such as optical fibers, charge coupled device cameras, photodiodes, or the like. The collected optical emissions are analyzed to determine whether or not an optical signature of a plasma instability exists in the collected optical emissions. Upon determining that the optical signature of the plasma instability does exist in the collected optical emissions, at least one plasma generation parameter is adjusted to mitigate formation of the plasma instability.


A wafer is positioned on a wafer support apparatus beneath an electrode such that a plasma generation region exists between the wafer and the electrode. Radiofrequency signals of a first signal frequency are supplied to the plasma generation region to generate a plasma within the plasma generation region. Formation of a plasma instability is detected within the plasma based on supply of the radiofrequency signals of the first signal frequency. After detecting formation of the plasma instability, radiofrequency signals of a second signal frequency are supplied to the plasma generation region in lieu of the radiofrequency signals of the first signal frequency to generate the plasma. The second signal frequency is greater than the first signal frequency and is set to cause a reduction in ion energy within the plasma and a corresponding reduction in secondary electron emission from the wafer caused by ion interaction with the wafer.


An apparatus for supporting a wafer during a plasma processing operation includes a pedestal configured to have bottom surface and a top surface and a column configured to support the pedestal at a central region of the bottom surface of the pedestal. An electrical insulating layer is disposed over the top surface of the pedestal. An electrically conductive layer is disposed over the top surface of the electrical insulating layer. At least three electrically conductive support structures are distributed on the electrically conductive layer. The at least three support structures are configured to interface with a bottom surface of a wafer to physically support the wafer and electrically connect to the wafer. An electrical connection extends from the electrically conductive layer to connect with a positive terminal of a direct current power supply at a location outside of the pedestal.


An edge ring assembly is provided, including: an upper edge ring configured to surround an electrostatic chuck (ESC), the ESC having a top surface for supporting a substrate and an annular step surrounding the top surface, the annular step defining an annular shelf that is lower than the top surface, the upper edge ring being disposed above the annular shelf; a lower inner edge ring disposed below the upper edge ring in the annular step and disposed over the annular shelf, the lower inner edge ring being defined from an electrically conductive material, the lower inner edge ring being electrically insulated from the ESC; a lower outer edge ring surrounding the inner edge ring, the lower outer edge ring being disposed below the upper edge ring in the annular step and disposed over the annular shelf, the lower outer edge ring being defined from an electrically insulating material.


Patent
Lam Research Corp. | Date: 2017-01-25

Methods for depositing extremely low resistivity tungsten in semiconductor processing are disclosed herein. Methods involve annealing the substrate at various times during the tungsten deposition process to achieve uniform tungsten layers with substantially lower resistivity.


Methods of selectively inhibiting deposition of silicon-containing films deposited by atomic layer deposition are provided. Selective inhibition involves exposure of an adsorbed layer of a silicon-containing precursor to a hydrogen-containing inhibitor, and in some instances, prior to exposure of the adsorbed layer to a second reactant. Exposure to a hydrogen-containing inhibitor may be performed with a plasma, and methods are suitable for selective inhibition in thermal or plasma enhanced atomic layer deposition of silicon-containing films.


Provided herein are methods of depositing fluorine-free tungsten by sequential CVD pulses, such as by alternately pulsing a chlorine-containing tungsten precursor and hydrogen in cycles of temporally separated pulses, without depositing a tungsten nucleation layer. Methods also include depositing tungsten directly on a substrate surface using alternating pulses of a chlorine-containing tungsten precursor and hydrogen without treating the substrate surface.


Grant
Agency: European Commission | Branch: H2020 | Program: ECSEL-IA | Phase: ECSEL-02-2014 | Award Amount: 139.30M | Year: 2015

The proposed pilot line project WAYTOGO FAST objective is to leverage Europe leadership in Fully Depleted Silicon on Insulator technology (FDSOI) so as to compete in leading edge technology at node 14nm and beyond preparing as well the following node transistor architecture. Europe is at the root of this breakthrough technology in More Moore law. The project aims at establishing a distributed pilot line between 2 companies: - Soitec for the fabrication of advanced engineered substrates (UTBB: Ultra Thin Body and BOx (buried oxide)) without and with strained silicon top film. - STMicroelectronics for the development and industrialization of state of the art FDSOI technology platform at 14nm and beyond with an industry competitive Power-Performance-Area-Cost (PPAC) trade-off. The project represents the first phase of a 2 phase program aiming at establishing a 10nm FDSOI technology for 2018-19. A strong added value network is created across this project to enhance a competitive European value chain on a European breakthrough and prepare next big wave of electronic devices. The consortium gathers a large group of partners: academics/institutes, equipment and substrate providers, semiconductor companies, a foundry, EDA providers, IP providers, fabless design houses, and a system manufacturer. E&M will contribute to the objective of installing a pilot line capable of manufacturing both advanced SOI substrates and FDSOI CMOS integrated circuits at 14nm and beyond. Design houses and electronics system manufacturer will provide demonstrator and enabling IP, to spread the FDSOI technology and establish it as a standard in term of leading edge energy efficient CMOS technology for a wide range of applications battery operated (consumer , healthcare, Internet of things) or not. Close collaboration between the design activities and the technology definition will tailor the PPAC trade-off of the next generation of technology to the applications needs.


Grant
Agency: European Commission | Branch: H2020 | Program: ECSEL-IA | Phase: ECSEL-02-2014 | Award Amount: 181.08M | Year: 2015

The SeNaTe project is the next in a chain of thematically connected ENIAC JU KET pilot line projects which are associated with 450mm/300mm development for the 12nm and 10nm technology nodes. The main objective is the demonstration of the 7nm IC technology integration in line with the industry needs and the ITRS roadmap on real devices in the Advanced Patterning Center at imec using innovative device architecture and comprising demonstration of a lithographic platform for EUV and immersion technology, advanced process and holistic metrology platforms, new materials and mask infrastructure. A lithography scanner will be developed based on EUV technology to achieve the 7nm module patterning specification. Metrology platforms need to be qualified for N7s 1D, 2D and 3D geometries with the appropriate precision and accuracy. For the 7nm technology modules a large number of new materials will need to be introduced. The introduction of these new materials brings challenges for all involved processes and the related equipment set. Next to new deposition processes also the interaction of the involved materials with subsequent etch, clean and planarization steps will be studied. Major European stakeholders in EUV mask development will collaboratively work together on a number of key remaining EUV mask issues. The first two years of the project will be dedicated to find the best options for patterning, device performance, and integration. In the last year a full N7 integration with electrical measurements will be performed to enable the validation of the 7nm process options for a High Volume Manufacturing. The SeNaTe project relates to the ECSEL work program topic Process technologies More Moore. It addresses and targets as set out in the MASP at the discovery of new Semiconductor Process, Equipment and Materials solutions for advanced CMOS processes that enable the nano-structuring of electronic devices with 7nm resolution in high-volume manufacturing and fast prototyping.

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