Fremont, CA, United States
Fremont, CA, United States

Lam Research Corporation is an American corporation that engages in the design, manufacture, marketing, and service of semiconductor processing equipment used in the fabrication of integrated circuits. Its products include etch systems, including dielectric and conductor etch, chemical vapor deposition , plasma-enhanced chemical vapor deposition , physical vapor deposition , electrochemical deposition , ultraviolet thermal processing , and resist strip and surface preparation, as well as synergy cleaning products. The company markets its products and services primarily to companies involved in the production of semiconductors in the United States, Europe, Asia Pacific, Korea, and Japan. Lam Research Corporation was founded in 1980 by Dr. David K. Lam and is headquartered in Fremont, California. Wikipedia.


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An edge ring assembly is provided, including: an upper edge ring configured to surround an electrostatic chuck (ESC), the ESC having a top surface for supporting a substrate and an annular step surrounding the top surface, the annular step defining an annular shelf that is lower than the top surface, the upper edge ring being disposed above the annular shelf; a lower inner edge ring disposed below the upper edge ring in the annular step and disposed over the annular shelf, the lower inner edge ring being defined from an electrically conductive material, the lower inner edge ring being electrically insulated from the ESC; a lower outer edge ring surrounding the inner edge ring, the lower outer edge ring being disposed below the upper edge ring in the annular step and disposed over the annular shelf, the lower outer edge ring being defined from an electrically insulating material.


Patent
Lam Research Corp. | Date: 2017-02-08

A method for modeling cable loss is described. The method includes receiving a measurement of reverse power and forward power at a radio frequency (RF) generator. The method further includes computing theoretical power delivered to a matching network as a difference between the forward power and the reverse power and calculating a ratio of the reverse power to the forward power to generate an RF power reflection ratio. The method further includes identifying a cable power attenuation fraction based on a frequency of the RF generator and calculating a cable power loss as a function of the RF power reflection ratio, the cable power attenuation fraction, and the theoretical power. The method includes calculating actual power to be delivered to the impedance matching network based on the theoretical power and the cable power loss and sending the calculated actual power to the RF generator to generate an RF signal.


Patent
Lam Research Corp. | Date: 2016-10-13

A substrate support for supporting a substrate in a substrate processing system includes a plurality of thermal elements. The thermal elements are arranged in one or more thermal zones, and each of the thermal zones includes at least one of the thermal elements. Each of the thermal elements includes a first resistive material having a positive thermal coefficient of resistance and a second resistive material having a negative thermal coefficient of resistance. The second resistive material is electrically connected to the first material. At least one of the first resistive material and the second resistive material of each of the thermal elements is electrically connected to a power supply to receive power, and each of the thermal elements heats a respective one of the thermal zones based on the received power. At least one ceramic layer is arranged adjacent to the thermal elements.


Disclosed is an electrode assembly (200) for a plasma reaction chamber used in semiconductor substrate processing comprising a backing member (230) having a bonding surface (227), the backing member (230); an electrode (220) having a lower surface on one side and a bonding surface (225) on the other side; wherein either the backing member (230) or the electrode has a recess. The bonding material (160) is confined to the at least one recess (280) or at least one spacer (281) is provided to maintain a gap between the bonding surfaces of the backing member and the electrode, and a bonding material (160) between the bonding surfaces (225, 282) of the backing member (230) and the electrode (220). A method of manufacturing an electrode assembly is further disclosed.


A tray for storing minimum contact area (MCA) components of a substrate processing system includes a first compartment including at least one of a first lift pin tray and a first plurality of holes. The first lift pin tray includes a plurality of slots configured to retain lift pins of the substrate processing system. The first plurality of holes is configured to receive MCA pins of the substrate processing system. A first cup is arranged adjacent to the first compartment. The first cup includes a wall at least partially surrounding the first cup, the wall separates the first cup from the first compartment, and an upper edge of the wall extends above a bottom surface of the first compartment.


A gas injector for a substrate processing system includes a first injector housing including a base portion defining a first gas flow channel; a projecting portion extending from the base portion; and a second gas flow channel extending through the base portion and the projecting portion. The gas injector includes a second injector housing including a first cavity including a first opening, a second opening and a first plurality of gas through holes arranged around the second opening. The first gas flow channel communicates with the first plurality of gas through holes. The second injector housing includes a second cavity that includes a second plurality of gas through holes and that extends from the second opening of the first cavity. The second gas flow channel communicates with the second plurality of gas through holes. Gas in the first and second gas flow channels flows into a processing chamber without mixing.


A system and method monitoring a plasma with an optical sensor to determine the operations of a pulsed RF signal for plasma processing including a plasma chamber with an optical sensor directed toward a plasma region. An RF generator coupled to the plasma chamber through a match circuit. An RF timing system coupled to the RF generator. A system controller is coupled to the plasma chamber, the RF generator, the optical sensor, the RF timing system and the match circuit. The system controller includes a central processing unit, a memory system, a set of RF generator settings and an optical pulsed plasma analyzer coupled to the optical sensor and being capable to determine a timing of a change in state of an optical emission received in the optical sensor and/or a set of amplitude statistics corresponding to an amplitude of the optical emission received in the optical sensor.


A system and method of identifying a selected process point in a multi-mode pulsing process includes applying a multi-mode pulsing process to a selected wafer in a plasma process chamber, the multi-mode pulsing process including multiple cycles, each one of the cycles including at least one of multiple, different phases. At least one process output variable is collected for a selected at least one of the phases, during multiple cycles for the selected wafer. An envelope and/or a template of the collected at least one process output variable can be used to identify the selected process point. A first trajectory for the collected process output variable of a previous phase can be compared to a second trajectory of the process output variable of the selected phase. A multivariate analysis statistic of the second trajectory can be calculated and used to identify the selected process point.


Grant
Agency: European Commission | Branch: H2020 | Program: ECSEL-IA | Phase: ECSEL-02-2014 | Award Amount: 139.30M | Year: 2015

The proposed pilot line project WAYTOGO FAST objective is to leverage Europe leadership in Fully Depleted Silicon on Insulator technology (FDSOI) so as to compete in leading edge technology at node 14nm and beyond preparing as well the following node transistor architecture. Europe is at the root of this breakthrough technology in More Moore law. The project aims at establishing a distributed pilot line between 2 companies: - Soitec for the fabrication of advanced engineered substrates (UTBB: Ultra Thin Body and BOx (buried oxide)) without and with strained silicon top film. - STMicroelectronics for the development and industrialization of state of the art FDSOI technology platform at 14nm and beyond with an industry competitive Power-Performance-Area-Cost (PPAC) trade-off. The project represents the first phase of a 2 phase program aiming at establishing a 10nm FDSOI technology for 2018-19. A strong added value network is created across this project to enhance a competitive European value chain on a European breakthrough and prepare next big wave of electronic devices. The consortium gathers a large group of partners: academics/institutes, equipment and substrate providers, semiconductor companies, a foundry, EDA providers, IP providers, fabless design houses, and a system manufacturer. E&M will contribute to the objective of installing a pilot line capable of manufacturing both advanced SOI substrates and FDSOI CMOS integrated circuits at 14nm and beyond. Design houses and electronics system manufacturer will provide demonstrator and enabling IP, to spread the FDSOI technology and establish it as a standard in term of leading edge energy efficient CMOS technology for a wide range of applications battery operated (consumer , healthcare, Internet of things) or not. Close collaboration between the design activities and the technology definition will tailor the PPAC trade-off of the next generation of technology to the applications needs.


Grant
Agency: European Commission | Branch: H2020 | Program: ECSEL-IA | Phase: ECSEL-02-2014 | Award Amount: 181.08M | Year: 2015

The SeNaTe project is the next in a chain of thematically connected ENIAC JU KET pilot line projects which are associated with 450mm/300mm development for the 12nm and 10nm technology nodes. The main objective is the demonstration of the 7nm IC technology integration in line with the industry needs and the ITRS roadmap on real devices in the Advanced Patterning Center at imec using innovative device architecture and comprising demonstration of a lithographic platform for EUV and immersion technology, advanced process and holistic metrology platforms, new materials and mask infrastructure. A lithography scanner will be developed based on EUV technology to achieve the 7nm module patterning specification. Metrology platforms need to be qualified for N7s 1D, 2D and 3D geometries with the appropriate precision and accuracy. For the 7nm technology modules a large number of new materials will need to be introduced. The introduction of these new materials brings challenges for all involved processes and the related equipment set. Next to new deposition processes also the interaction of the involved materials with subsequent etch, clean and planarization steps will be studied. Major European stakeholders in EUV mask development will collaboratively work together on a number of key remaining EUV mask issues. The first two years of the project will be dedicated to find the best options for patterning, device performance, and integration. In the last year a full N7 integration with electrical measurements will be performed to enable the validation of the 7nm process options for a High Volume Manufacturing. The SeNaTe project relates to the ECSEL work program topic Process technologies More Moore. It addresses and targets as set out in the MASP at the discovery of new Semiconductor Process, Equipment and Materials solutions for advanced CMOS processes that enable the nano-structuring of electronic devices with 7nm resolution in high-volume manufacturing and fast prototyping.

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