Fremont, CA, United States
Fremont, CA, United States

Lam Research Corporation is an American corporation that engages in the design, manufacture, marketing, and service of semiconductor processing equipment used in the fabrication of integrated circuits. Its products include etch systems, including dielectric and conductor etch, chemical vapor deposition , plasma-enhanced chemical vapor deposition , physical vapor deposition , electrochemical deposition , ultraviolet thermal processing , and resist strip and surface preparation, as well as synergy cleaning products. The company markets its products and services primarily to companies involved in the production of semiconductors in the United States, Europe, Asia Pacific, Korea, and Japan. Lam Research Corporation was founded in 1980 by Dr. David K. Lam and is headquartered in Fremont, California. Wikipedia.


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An edge ring assembly is provided, including: an upper edge ring configured to surround an electrostatic chuck (ESC), the ESC having a top surface for supporting a substrate and an annular step surrounding the top surface, the annular step defining an annular shelf that is lower than the top surface, the upper edge ring being disposed above the annular shelf; a lower inner edge ring disposed below the upper edge ring in the annular step and disposed over the annular shelf, the lower inner edge ring being defined from an electrically conductive material, the lower inner edge ring being electrically insulated from the ESC; a lower outer edge ring surrounding the inner edge ring, the lower outer edge ring being disposed below the upper edge ring in the annular step and disposed over the annular shelf, the lower outer edge ring being defined from an electrically insulating material.


Grant
Agency: Cordis | Branch: H2020 | Program: ECSEL-IA | Phase: ECSEL-02-2014 | Award Amount: 139.30M | Year: 2015

The proposed pilot line project WAYTOGO FAST objective is to leverage Europe leadership in Fully Depleted Silicon on Insulator technology (FDSOI) so as to compete in leading edge technology at node 14nm and beyond preparing as well the following node transistor architecture. Europe is at the root of this breakthrough technology in More Moore law. The project aims at establishing a distributed pilot line between 2 companies: - Soitec for the fabrication of advanced engineered substrates (UTBB: Ultra Thin Body and BOx (buried oxide)) without and with strained silicon top film. - STMicroelectronics for the development and industrialization of state of the art FDSOI technology platform at 14nm and beyond with an industry competitive Power-Performance-Area-Cost (PPAC) trade-off. The project represents the first phase of a 2 phase program aiming at establishing a 10nm FDSOI technology for 2018-19. A strong added value network is created across this project to enhance a competitive European value chain on a European breakthrough and prepare next big wave of electronic devices. The consortium gathers a large group of partners: academics/institutes, equipment and substrate providers, semiconductor companies, a foundry, EDA providers, IP providers, fabless design houses, and a system manufacturer. E&M will contribute to the objective of installing a pilot line capable of manufacturing both advanced SOI substrates and FDSOI CMOS integrated circuits at 14nm and beyond. Design houses and electronics system manufacturer will provide demonstrator and enabling IP, to spread the FDSOI technology and establish it as a standard in term of leading edge energy efficient CMOS technology for a wide range of applications battery operated (consumer , healthcare, Internet of things) or not. Close collaboration between the design activities and the technology definition will tailor the PPAC trade-off of the next generation of technology to the applications needs.


Grant
Agency: Cordis | Branch: H2020 | Program: ECSEL-IA | Phase: ECSEL-02-2014 | Award Amount: 181.08M | Year: 2015

The SeNaTe project is the next in a chain of thematically connected ENIAC JU KET pilot line projects which are associated with 450mm/300mm development for the 12nm and 10nm technology nodes. The main objective is the demonstration of the 7nm IC technology integration in line with the industry needs and the ITRS roadmap on real devices in the Advanced Patterning Center at imec using innovative device architecture and comprising demonstration of a lithographic platform for EUV and immersion technology, advanced process and holistic metrology platforms, new materials and mask infrastructure. A lithography scanner will be developed based on EUV technology to achieve the 7nm module patterning specification. Metrology platforms need to be qualified for N7s 1D, 2D and 3D geometries with the appropriate precision and accuracy. For the 7nm technology modules a large number of new materials will need to be introduced. The introduction of these new materials brings challenges for all involved processes and the related equipment set. Next to new deposition processes also the interaction of the involved materials with subsequent etch, clean and planarization steps will be studied. Major European stakeholders in EUV mask development will collaboratively work together on a number of key remaining EUV mask issues. The first two years of the project will be dedicated to find the best options for patterning, device performance, and integration. In the last year a full N7 integration with electrical measurements will be performed to enable the validation of the 7nm process options for a High Volume Manufacturing. The SeNaTe project relates to the ECSEL work program topic Process technologies More Moore. It addresses and targets as set out in the MASP at the discovery of new Semiconductor Process, Equipment and Materials solutions for advanced CMOS processes that enable the nano-structuring of electronic devices with 7nm resolution in high-volume manufacturing and fast prototyping.


Patent
Lam Research Corp. | Date: 2016-05-18

An apparatus for processing a substrate is provided. A chamber wall forms a processing chamber cavity. A substrate support for supporting the substrate is within the processing chamber cavity. A gas inlet for providing gas into the processing chamber is above a surface of the substrate. A window for passing RF power into the processing chamber cavity comprises a ceramic or quartz window body and a coating of at least one of erbium oxide, erbium fluoride, samarium oxide, samarium fluoride, thulium oxide thulium fluoride, gadolinium oxide, or gadolinium fluoride on a surface of the ceramic window body. A coil is outside of the processing chamber cavity, wherein the window is between the processing chamber cavity and the coil.


Patent
Lam Research Corp. | Date: 2016-08-22

A plasma source includes a ring plasma chamber, a primary winding around an exterior of the ring plasma chamber, multiple ferrites, wherein the ring plasma chamber passes through each of the ferrites and multiple plasma chamber outlets coupling the plasma chamber to a process chamber. Each one of the plasma chamber outlets having a respective plasma restriction. A system and method for generating a plasma are also described.


Patent
Lam Research Corp. | Date: 2016-06-03

Provided herein are ALE methods of removing III-V materials such as gallium nitride (GaN) and related apparatus. In some embodiments, the methods involve exposing the III-V material to a chlorine-containing plasma without biasing the substrate to form a modified III-V surface layer; and applying a bias voltage to the substrate while exposing the modified III-V surface layer to a plasma to thereby remove the modified III-V surface layer. The disclosed methods are suitable for a wide range of applications, including etching processes for trenches and holes, fabrication of HEMTs, fabrication of LEDs, and improved selectivity in etching processes.


Patent
Lam Research Corp. | Date: 2016-08-15

Methods for etching a substrate in a plasma processing chamber having at least a primary plasma generating region and a secondary plasma generating region separated from said primary plasma generating region by a semi-barrier structure. The method includes generating a primary plasma from a primary feed gas in the primary plasma generating region. The method also includes generating a secondary plasma from a secondary feed gas in the secondary plasma generating region to enable at least some species from the secondary plasma to migrate into the primary plasma generating region. The method additionally includes etching the substrate with the primary plasma after the primary plasma has been augmented with migrated species from the secondary plasma.


Patent
Lam Research Corp. | Date: 2016-05-31

In one aspect, several apparatuses are described that allow a processing chamber designed for plasma-enhanced chemical vapor deposition on 300 mm wafers to be performed on 200 mm wafers. More specifically, a modified pedestal, carrier plate, and showerhead are described that have been designed for 200 mm wafers and are compatible with 300 mm wafer processing chambers. It has further been observed that deposited films using the modified 200 mm apparatuses are comparable in quality with films deposited with the 300 mm devices they replace.


Patent
Lam Research Corp. | Date: 2016-06-09

Systems and methods for processing a substrate include arranging a substrate including a film layer on a substrate support in a processing chamber. The film layer includes a boron doped carbon hard mask. A plasma gas mixture is supplied and includes molecular hydrogen, nitrogen trifluoride, and a gas selected from a group consisting of carbon dioxide and nitrous oxide. Plasma is struck in the processing chamber or supplied to the processing chamber for a predetermined stripping period. The plasma strips the film layer during the predetermined stripping period and the plasma is extinguished.


Patent
Lam Research Corp. | Date: 2016-09-09

Systems and methods controlling ion energy within a plasma chamber are described. One of the systems includes an upper electrode coupled to a sinusoidal RF generator for receiving a sinusoidal signal and a nonsinusoidal RF generator for generating a nonsinusoidal signal. The system further includes a power amplifier coupled to the nonsinusoidal RF generator. The power amplifier is used for amplifying the nonsinusoidal signal to generate an amplified signal. The system includes a filter coupled to the power amplifier. The filter is used for filtering the amplified signal using a filtering signal to generate a filtered signal. The system includes a chuck coupled to the filter. The chuck faces at least a portion of the upper electrode and includes a lower electrode. The lower electrode is used for receiving the filtered signal to facilitate achieving ion energy at the chuck to be between a lower threshold and an upper threshold.

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