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Bahri N.,University of Sfax | Bahri N.,Laboratory of Electronics and Information Technology | Werda I.,University of Sfax | Werda I.,Laboratory of Electronics and Information Technology | And 10 more authors.
International Review on Computers and Software | Year: 2013

Real-time H.264/AVC high definition video encoding represents a challenging workload to most existing programmable processors. The new technologies of programmable processors such as Graphic Processor Unit (GPU) and multicore Digital signal Processor (DSP) offer a very promising solution to overcome these constraints. In this paper, an optimized implementation of H264/AVC video encoder on a single core among the six cores of TMS320C6472 DSP for Common Intermediate Format (CIF) (352×288) resolution is presented in order to move afterwards to a multicore implementation for standard and high definitions (SD,HD). Algorithmic optimization is applied to the intra prediction module to reduce the computational time. Furthermore, based on the DSP architectural features, various structural and hardware optimizations are adopted to minimize external memory access. The parallelism between CPU processing and data transfers is fully exploited using an Enhanced Direct Memory Access controller (EDMA). Experimental results show that the whole proposed optimizations, on a single core running at 700 MHz for CIF resolution, improve the encoding speed by up to 42.91%. They allow reaching the real-time encoding 25 f/s without inducing any Peak Signal to Noise Ratio (PSNR) degradation or bit-rate increase and make possible to achieve real time implementation for SD and HD resolutions when exploiting multicore features. © 2013 Praise Worthy Prize S.r.l. - All rights reserved.

Boudabous A.,Laboratory of Electronics and Information Technology | Ben Atitallah A.,Laboratory of Electronics and Information Technology | Ben Atitallah A.,University of Bordeaux 1 | Khriji L.,Sultan Qaboos University | And 2 more authors.
International Arab Journal of Information Technology | Year: 2010

A new code sign implementation of vector median rational hybrid filter based on efficient hardware/software implementation is introduced and applied to colour image filtering problems. This filter is used essentially to remove impulsive and Gaussian noise in colour images. In our design we start by implementing the software solution in system on programmable chip context using NIOS-II softcore processor and μClinux as operating system. We evaluate the execution time of the whole filtering process. Than we add a hardware accelerator part. This latter is implemented using fast parallel architecture. Compared to the software solution results, the use of the hardware accelerator improves clearly the filtering speed and maintains the good filtering quality as shown by simulations.

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