Fendler M.,Laboratory for Electronics and Information Techniques |
Marion F.,Laboratory for Electronics and Information Techniques |
Patrice D.S.,Laboratory for Electronics and Information Techniques |
Mandrillon V.,Laboratory for Electronics and Information Techniques |
And 2 more authors.
IEEE Transactions on Components, Packaging and Manufacturing Technology | Year: 2011
Flip-chip is a high-density and highly reliable interconnection technology, which is widely used for the fabrication of infrared complementary metal-oxide-semiconductor imagers. In order to increase the format and the resolution of staring arrays to 2000 × 2000 pixels or even larger complexities, while keeping substrate dimensions and device cost low, there is a general trend in reducing pixel size. But this results in a very challenging process control for ultrafine-pitch and high-count flip-chip bonding technology. A new room-temperature insertion technology has been proposed and developed to alleviate most of these issues. It overcomes the planarity and thermal mismatch issues of this heterogeneous assembly made of cadmium mercury telluride detectors hybridized on silicon read-out circuits while reducing the bonding thermocompression forces and the hybridization temperature. The technological preparation of the assembled devices is described in this paper. A process characterization, using a modified nanoindenter with instrumentation for single tip insertion, has been achieved to evaluate insertion mechanical parameters. This paper gives also the first measured interconnection yield and vertical access resistance of 2000 × 2000 hybridized arrays of 10 μm pitch, fabricated using the proposed insertion flip-chip technique. Connection results are discussed, and a comparative study proves that parallelism during insertion is a key parameter. When providing a perfect parallelism control with advanced new flip-chip bonders, the microtip insertion technique is scalable to complexities of over 4 million connections at very fine pitch. Moreover, this new low-temperature insertion concept could possibly be applied to 3-D interstrata interconnections for electronic devices. Indeed, it avoids the issues caused by cumulative high-temperature cycles, which are typical of more conventional processes. © 2011-2012 IEEE. Source