Sliwinski P.,Wroclaw University of Technology |
Berezowski K.,Wroclaw University of Technology |
Wachel P.,Wroclaw University of Technology |
Sicard G.,Wroclaw University of Technology |
Fesquet L.,Laboratoire TIMA
IFAC Proceedings Volumes (IFAC-PapersOnline) | Year: 2013
Two algorithms recovering an input nonlinearity in a nonlinear distributed element modeled as a Hammerstein system are proposed. The ?rst is based on the empirical distribution function while the other on the empirical Haar orthogonal series. Both algorithms self-adjust their accuracy to a local density of the input measurements. © IFAC.
Steininger A.,Vienna University of Technology |
Veeravalli V.S.,Vienna University of Technology |
Alexandrescu D.,Pierre Mendes-France University |
Costenaro E.,Pierre Mendes-France University |
Anghel L.,Laboratoire TIMA
2014 32nd IEEE International Conference on Computer Design, ICCD 2014 | Year: 2014
Asynchronous circuits exhibit considerable advantages over their synchronous counterparts, like lower dynamic power and inherent variation tolerance, which makes them increasingly interesting. Their fault-tolerance behavior, however, is not yet fully explored. In particular, temporal masking, as seen with synchronous circuits, seems to be completely non-existent in asynchronous logic. Instead, there seem to be other masking mechanisms in the control structure that establish an extra barrier for transient fault propagation. In this paper we will explore these masking mechanisms in a qualitative as well as quantitative manner. To this end we first analyze the behavior of a Muller C-element, one fundamental building block in asynchronous designs. In a next step we evaluate the behavior of a chain of these elements, forming a so-called Muller pipeline, the basic control structure of many asynchronous designs, under transient faults. To validate our theoretical findings we inject radiation induced single event transients (SETs) in an extensive simulation campaign. The results show that the SET susceptibility of the Muller pipeline is indeed state dependent. This knowledge can be leveraged to improve, e.g., the radiation hardness of asynchronous circuits by preferring the more robust states in their design wherever possible. © 2014 IEEE.
Beyrouthy T.,Laboratoire TIMA |
Fesquet L.,Laboratoire TIMA
International Journal of Reconfigurable Computing | Year: 2013
This paper presents an FPGA tech-mapping algorithm dedicated to security applications. The objective is to implement - on a full-custom asynchronous FPGA - secured functions that need to be robust against side-channel attacks (SCAs). The paper briefly describes the architecture of this FPGA that has been designed and prototyped in CMOS 65 nm to target various styles of asynchronous logic including 2-phase and 4-phase communication protocols and 1-of-n data encoding. This programmable architecture is designed to be electrically balanced in order to fit the security requirements. It allows fair comparisons between different styles of asynchronous implementations. In order to illustrate the FPGA flexibility and security, a case study has been implemented in 2-phase and 4-phase Quasi-Delay-Insensitive (QDI) logic. © 2013 Taha Beyrouthy and Laurent Fesquet.
Foucard G.,Laboratoire TIMA |
Peronnard P.,Laboratoire TIMA |
Velazco R.,Laboratoire TIMA
Journal of Electronic Testing: Theory and Applications (JETTA) | Year: 2011
This paper presents experimental results putting in evidence the potential weaknesses of a state-of-the-art fault tolerance strategy, the Triple Modular Redundancy (TMR), when implemented in SRAM-based FPGAs. HW/SW fault injection campaigns and accelerated radiation ground tests were performed to quantify the number of faults, Single Event Upsets (SEUs) required to obtain such critical failures. © Springer Science+Business Media, LLC 2011.
Bonnoit T.,Laboratoire TIMA |
Nicolaidis M.,Laboratoire TIMA |
Zergainoh N.-E.,Laboratoire TIMA
Journal of Electronic Testing: Theory and Applications (JETTA) | Year: 2013
Drastic device shrinking, power supply reduction, increasing complexity and increasing operating speeds affect adversely the reliability of nowadays Integrate Circuits (ICs). In many modern designs, embedded memories occupy the largest part of the die and comprise the large majority of transistors. Furthermore, memories are designed as tight as allowed by the process, and are therefore more prone to failures than other circuits. Error correcting codes (ECCs) are an efficient mean for protecting memories against failures. A major drawback of ECCs is the speed penalty induced by the encoding and decoding circuits. In this paper, we present an architecture enabling implementing ECCs without speed penalty. Furthermore, as the manual implementation of this solution is impractical for complex System-on-Chips (SoCs), we propose an algorithm and a set of generic rules allowing automatic insertion of the delay-free ECCs in any complex architecture at Register Transfer Level (RTL). With respect to a naive insertion in the design of the new architecture, the algorithm enable up to 20 % hardware reduction. The Finite State Machines (FSM) that controls the new ECC architecture is also generated automatically. Experimental evaluations show that the hardware overhead of the speed penalty free ECCs protected memory compared to a standard implementation of ECC protected memory is about 2.5 % with an additional power consumption of 6 %. © 2013 Springer Science+Business Media New York.