Laboratoire delectronique et micro electronique Laboratory IT06

Monastir, Tunisia

Laboratoire delectronique et micro electronique Laboratory IT06

Monastir, Tunisia
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Benhadjyoussef N.,Laboratoire delectronique et micro electronique Laboratory IT06 | Elhadjyoussef W.,Laboratoire delectronique et micro electronique Laboratory IT06 | Machhout M.,Laboratoire delectronique et micro electronique Laboratory IT06 | Torki K.,Laboratoire delectronique et micro electronique Laboratory IT06 | Tourki R.,Circuits Multi Project
International Review on Computers and Software | Year: 2013

With the information breaches growing nowadays, the demand for serious efforts towards ensuring security in embedded systems becomes more important. The successful employment of these embedded systems for e-commerce, transaction banking, mobile commerce, etc, depend on the reliability of the security solutions. Respecting the real-time performance and the resource-constrained target environment for the next-generation applications, the embedded system design have been a theme of serious study these last few years. This paper presents a hardware crypto-processor for the arising issue of information security in embedded system. This crypto-processor can be used for various security applications such as smartcards, network routers, wireless systems, etc. The proposed 32-bit processor executes various IP crypto cores like hash function, private and public key operations, Random Number generator and other application programs such as user authentication. The hardware description is done in ModelSim using VHDL and synthesized using Synopsys Design Compiler. Furthermore, the proposed crypto-processor is implemented using Xilinx XC5VFX70t FPGA device and an ASIC CMOS 40 nm technology. The results show a high performance, confirming the efficiency of the processor. We have carefully chosen the dedicated algorithms to reduce the required memory resources while respecting the necessary runtime within reasonable limits. The proposed crypto-processor has a total core area of 1.35 mm2 and can achieve an operating system frequency of 500 MHz. The estimated power of the chip was 4,6 mW at 10 MHz. © 2013 Praise Worthy Prize S.r.l. - All rights reserved.


Benhadjyoussef N.,Laboratoire delectronique et micro electronique Laboratory IT06 | Elhadjyoussef W.,Laboratoire delectronique et micro electronique Laboratory IT06 | Machhout M.,Laboratoire delectronique et micro electronique Laboratory IT06 | Tourki R.,Laboratoire delectronique et micro electronique Laboratory IT06
International Review on Modelling and Simulations | Year: 2013

The performance evaluation of cryptographic algorithms has guided to serious studies of its implementations. The efficiency of these algorithms is improved by applying good design rules adapted to devices and to its resources constraints. In this paper, we present a careful study of three possible designs of the Advanced Encryption Standard (AES) targeting 32-bit embedded system; we examined AES implementations which use arithmetic properties of the AES S-box and structures based on hardware look-up tables. We have analyzed and compared different characteristics like clock frequency, occupancy area, and power consumption of these implementations. The resulting designs are implemented using Xilinx XC5VFX70t FPGA device and an ASIC CMOS 40 nm technology. Our results show that AES implementation based on hardware look-up table shows the lowest power consumption and highest frequency. The AES implementations which use arithmetic properties of the S-box are characterized by the smallest silicon area. © 2013 Praise Worthy Prize S.r.l. - All rights reserved.

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