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Agency: Cordis | Branch: H2020 | Program: ECSEL-IA | Phase: ECSEL-02-2014 | Award Amount: 87.61M | Year: 2015

The key objective of PowerBase Enhanced substrates and GaN pilot lines enabling compact power applications is to ensure the availability of Electronic Components and Systems (ECS) for key markets and for addressing societal challenges, aiming at keeping Europe at the forefront of the technology development, bridging the gap between research and exploitation, creating economic and employment growth in the European Union. The project PowerBase aims to contribute to the industrial ambition of value creation in Europe and fully supports this vision by addressing key topics of ECSEL multi annual strategic plan 2014. By positioning PowerBase as innovation action a clear focus on exploitation of the expected result is primary goal. To expand the limits in current power semiconductor technologies the project focuses on setting up a qualified wide band gap GaN technology Pilot line, on expanding the limits of todays silicon based substrate materials for power semiconductors, improving manufacturing efficiency by innovative automation, setting up of a GaN compatible chip embedding pilot line and demonstrating innovation potential in leading compact power application domains. PowerBase is a project proposal with a vertical supply chain involved with contributions from partners in 7 European countries. This spans expertise from raw material research, process innovation, pilot line, assembly innovation and pilot line up to various application domains representing enhanced smart systems. The supporting partners consist of market leaders in their domain, having excellent technological background, which are fully committed to achieve the very challenging project goals. The project PowerBase aims to have significant impact on mart regions. High tech jobs in the area of semiconductor technologies and micro/nano electronics in general are expressed core competences of the regions Austria: Carinthia, Styria, Germany: Sachsen, Bavaria and many other countries/ regions involved.

Kolednik O.,Austrian Academy of Sciences | Zechner J.,Austrian Academy of Sciences | Zechner J.,Materials Center Leoben Forschung | Zechner J.,KAI Kompetenzzentrum Automobil und Industrieelektronik GmbH | Predan J.,University of Maribor
Scripta Materialia | Year: 2016

Retardation of fatigue crack growth rate due to the introduction of thin, compliant and/or soft interlayers is investigated. The mechanism is the reduction of the crack driving force in the interlayer. Fatigue tests are conducted on composites made of high-strength aluminum alloy as matrix and technically pure aluminum or adhesive as interlayer material. The adhesive interlayer causes an increase in fatigue life by a factor 20 or more, whereas the aluminum interlayer yields only a moderate improvement. Numerical simulations based on the configurational force concept are utilized for understanding. The results show new possibilities for the design of fatigue-resistant materials. © 2015 Elsevier Ltd. All rights reserved.

Agency: Cordis | Branch: H2020 | Program: ECSEL-IA | Phase: ECSEL-14-2015 | Award Amount: 61.99M | Year: 2016

Addressing European Policies for 2020 and beyond the Power Semiconductor and Electronics Manufacturing 4.0 (SemI40) project responds to the urgent need of increasing the competitiveness of the Semiconductor manufacturing industry in Europe through establishing smart, sustainable, and integrated ECS manufacturing. SemI40 will further pave the way for serving highly innovative electronic markets with products powered by microelectronics Made in Europe. Positioned as an Innovation Action it is the high ambition of SemI40 to implement technical solutions on TRL level 4-8 into the pilot lines of the industry partners. Challenging use cases will be implemented in real manufacturing environment considering also their technical, social and economic impact to the society, future working conditions and skills needed. Applying Industry 4.0, Big Data, and Industrial Internet technologies in the electronics field requires holistic and complex actions. The selected main objectives of SemI40 covered by the MASP2015 are: balancing system security and production flexibility, increase information transparency between fields and enterprise resource planning (ERP), manage critical knowledge for improved decision making and maintenance, improve fab digitalization and virtualization, and enable automation systems for agile distributed production. SemI40s value chain oriented consortium consists of 37 project partners from 5 European countries. SemI40 involves a vertical and horizontal supply chain and spans expertise and partners from raw material research, process and assembly innovation and pilot line, up to various application domains representing enhanced smart systems. Through advancing manufacturing of electronic components and systems, SemI40 contributes to safeguard more than 20.000 jobs of people directly employed in the participating facilities, and in total more than 300.000 jobs of people employed at all industry partners facilities worldwide.

Hasani R.M.,Vienna University of Technology | Haerle D.,KAI Kompetenzzentrum Automobil und Industrieelektronik GmbH | Grosu R.,Vienna University of Technology
2016 12th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2016 | Year: 2016

This paper introduces a black-box method for automatically learning an approximate but simulation-time efficient high-level abstraction of given analog integrated circuit (IC). The learned abstraction consists of a non-linear auto-regressive neural network with exogenous input (NARX), which is trained and validated from the input-output traces of the IC stimulated with particular inputs. We show the effectiveness of our approach on the power-up behavior and supply dependency of a CMOS band-gap reference (BGR) circuit. We discuss in detail the precision of the NARX abstraction, and show how this model can be used and implemented in testing of Analog ICs within the Cadence environment. By using our method one can automatically learn high-level abstractions of all the components of an Analog IC. This dramatically speeds up the transient simulation time of the Analog ICs. © 2016 IEEE.

Krivec S.,KAI Kompetenzzentrum Automobil und Industrieelektronik GmbH | Krivec S.,Vienna University of Technology | Detzel T.,Infineon Technologies | Buchmayr M.,Infineon Technologies | Hutter H.,Vienna University of Technology
Applied Surface Science | Year: 2010

The detection of Na in insulating samples by means of time of flight-secondary ion mass spectrometry (ToF-SIMS) depth profiling has always been a challenge. In particular the use of O2 + as sputter species causes a severe artifact in the Na depth distribution due to Na migration under the influence of an internal electrical filed. In this paper we address the influence of the sample temperature on this artifact. It is shown that the transport of Na is a dynamic process in concordance with the proceeding sputter front. Low temperatures mitigated the migration process by reducing the Na mobility in the target. In the course of this work two sample types have been investigated: (i) A Na doped PMMA layer, deposited on a thin SiO 2 film. Here, the incorporation behavior of Na into SiO2 during depth profiling is demonstrated. (ii) Na implanted into a thin SiO 2 film. By this sample type the migration behavior could be examined when defects, originating from the implantation process, are present in the SiO2 target. In addition, we propose an approach for the evaluation of an implanted Na profile, which is unaffected by the migration process. © 2010 Elsevier B.V. All rights reserved.

Smolka M.,KAI Kompetenzzentrum Automobil und Industrie Elektronik GmbH | Motz C.,Austrian Academy of Sciences | Detzel T.,Infineon Technologies | Robl W.,Infineon Technologies | And 4 more authors.
Review of Scientific Instruments | Year: 2012

The temperature dependent mechanical properties of the metallization of electronic power devices are studied in tensile tests on micron-sized freestanding copper beams at temperatures up to 400 °C. The experiments are performed in situ in a scanning electron microscope. This allows studying the micromechanical processes during the deformation and failure of the sample at different temperatures. © 2012 American Institute of Physics.

Koel V.,KAIKompetenzzentrum Automobil und Industrie Elektronik GmbH | Illing R.,Infineon Technologies | Glavanovics M.,KAIKompetenzzentrum Automobil und Industrie Elektronik GmbH | Atka A.,Slovak University of Technology in Bratislava
Microelectronics Journal | Year: 2010

The relevance of thermally non-linear silicon material models for transient thermal FEM simulations of smart power switches (SPS) is proved by a power silicon test device consisting of two power transistors and eleven integrated temperature sensors distributed over the silicon die. The test device is heated up by turning on an integrated power transistor in short-circuit for several milliseconds at two different initial temperatures. These thermal events correspond to a real situation that can occur in the application. The power dissipation in the power transistor is calculated from the measured source current and drain-source voltage, and subsequently used as an input to the FEM simulation. The temperature change on the test chip is measured by the integrated temperature sensors. An FEM model of the test chip encapsulated in a plastic package has been built in the FlexPDE simulator. The emphasis is put on the macroscopic modeling of the power transistor where an electro-thermal approach is reduced to a purely thermal one. Finally, the thermal events are simulated using FEM and compared to the temperature measurements. The results have shown that our modeling approach including non-linear properties of silicon can be used to investigate the thermal transients in SPS devices with high accuracy. © 2010 Elsevier Ltd. All rights reserved.

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