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Kulkarni R.,KLS Gogte Institute of Technology | Kulkarni S.Y.,M S Ramahai Institute Of Technology
11th IEEE India Conference: Emerging Trends and Innovation in Technology, INDICON 2014 | Year: 2015

The need to design and develop high performance and high speed VLSI systems such as NOCs in networking or SOCs in communication and computing has shifted the focus from traditional performance parameters towards the analysis of power consumption. In such devices managing the power among the domains of a system is of real concern. Hence, the low power design techniques namely: clock gating, power gating, dynamic voltage scaling and frequency scaling are of most important. In this paper the clock gating technique is applied to a 16-bit ALU. In the this work the ALU is divided into two functional units namely: Arithmetic unit and Logical Unit. The demultiplexer is used as a selector of the functional unit for which the clock is applied. The design is simulated using QuestaSim power aware simulator, implemented and synthesized using Precision synthesis tool on a Spartan 6 FPGA. Power analysis is carried out using Xilinx XPower analyzer. The design is tested for a wide band of frequencies from 1MHz to 5000MHz. The Clock and dynamic power reduction is observed for lower frequencies but for high frequency the target device has the limitation. The clock gating technique when applied to the design it is observed that the clock power is reduced by an average of 70% for lower frequencies and an average of 30% for higher frequencies. This reduction is at the cost increase in area by 2%. © 2014 IEEE. Source


Malladi S.,National Institute of Technology Karnataka | Malladi S.,KLS Gogte Institute of Technology | Isloor A.M.,National Institute of Technology Karnataka | Peethambar S.K.,Kuvempu University | And 2 more authors.
Arabian Journal of Chemistry | Year: 2014

A series of 2,5-disubstituted-1,3,4-oxadiazole derivatives bearing pyrazole moiety were synthesized by reacting various substituted pyrazole-4-carboxylic acids with different hydrazides in POCl3. All the synthesized compounds (4a-n) were characterized by IR, NMR, mass spectra and elemental analyses. Synthesized 1,3,4-oxadiazole derivatives were screened for their antibacterial activity against three different strains, namely Escherichia coli, Staphylococcus aureus and Pseudomonas aeruginosa, while antifungal activity was determined against three different strains Aspergillus flavus, Chrysosporium keratinophilum and Candida albicans. The investigation of antimicrobial screening revealed that compounds 4i and 4j exhibited excellent activity when compared with the standard drugs. © 2013 King Saud University. Source


Kulkarni R.,KLS Gogte Institute of Technology | Kulkarni S.Y.,M S Ramahai Institute Of Technology
2014 International Conference on Electronics and Communication Systems, ICECS 2014 | Year: 2014

Power dissipation is a bottleneck in the design of high speed synchronous systems operating at high frequency. Thus, clock signals have been a great source of power dissipation because of high frequency and heavy packet traffic in the network routers. Clock signals do not carry any information used for computation and only used for synchronization, but, the power dissipated is significant. In a Network Processor (NP) consisting of more than one processing elements (PE), not all are functioning at the same time, but connected to the clock signal dissipate power. Hence, the clock gating (CG) technique can to applied to these PEs. In this paper as a initial step to the design of such PEs the CG is applied to a 16-bit ALU. The design is simulated using QuestaSim power aware simulator, implemented and synthesized using Precision synthesis tool on a 45nm Spartan 6 FPGA. Power analysis is carried out using Xilinx XPower analyzer. Reduction in Clock and dynamic power is observed for lower frequencies but for high frequency the target device has the limitation. The design is optimized for power and area. © 2014 IEEE. Source


Kulkarni R.,KLS Gogte Institute of Technology | Kulkarni S.Y.,M S Ramahai Institute Of Technology
Proceedings of International Conference on Circuits, Communication, Control and Computing, I4C 2014 | Year: 2014

Power dissipation is a bottleneck in the design of low power electronic devices that, operate at high frequencies. Hence, the clock signal is a major source of power dissipation. The technique clock gating at the architecture level can be implemented to reduce the dynamic and clock power. In this paper, the authors aim at implementing, analyzing and comparing the various resource power using clock gating techniques to a 16-bit ALU on a 45nm SPARTANO FPGA board. The two clocking gates proposed and used in the design are namely: DEMUX and AND gate, which provide clock input to only one functional module that is either arithmetic or logical block, while the other is put OFF. The complete design is simulated using QuestaSim, synthesized using Precision tool and the power analysis is performed using Xpower analyzer of ISE13.2. The results obtained demonstrate that the clock, signal and the logic power for the two techniques is nearly same. While the IO and dynamic power using AND clocking gate has the power reduction of 50% and 45% respectively. Thus, the AND clock gating technique can be used in the design to optimize power and area. © 2014 IEEE. Source


Bekinal S.I.,KLS Gogte Institute of Technology | Jana S.,Bearings and Rotor Dynamics Laboratory
Journal of Tribology | Year: 2016

This work deals with generalized three-dimensional (3D) mathematical model to estimate the force and stiffness in axially, radially, and perpendicularly polarized passive magnetic bearings with "n" number of permanent magnet (PM) ring pairs. Coulombian model and vector approach are used to derive generalized equations for force and stiffness. Bearing characteristics (in three possible standard configurations) of permanent magnet bearings (PMBs) are evaluated using matlab codes. Further, results of the model are validated with finite element analysis (FEA) results for five ring pairs. Developed matlab codes are further utilized to determine only the axial force and axial stiffness in three stacked PMB configurations by varying the number of rings. Finally, the correlation between the bearing characteristics (PMB with only one and multiple ring pairs) is proposed and discussed in detail. The proposed mathematical model might be useful for the selection of suitable configuration of PMB as well as its optimization for geometrical parameters for high-speed applications. © Copyright 2016 by ASME. Source

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