Milpitas, CA, United States
Milpitas, CA, United States

KLA-Tencor Corporation is an American manufacturing company based in Milpitas, California. It supplies process control and yield management products for the semiconductor, data storage, LED, and other related nanoelectronics industries. The company's products, software and services are designed to help integrated circuit manufacturers manage yield throughout the entire fabrication process — from research and development to final volume production. Wikipedia.


Time filter

Source Type

A system, method and computer program product are provided for calibrating metrology tools. One or more design-of-experiments wafers is received for calibrating a metrology tool. A set of signals is collected by measuring the one or more wafers utilizing the metrology tool. A first transformation is determined to convert the set of signals to components, and a second transformation is determined to convert a set of reference signals to reference components. The set of reference signals is collected by measuring the one or more wafers utilizing a well-calibrated reference tool. A model is trained based on the reference components that maps the components to converted components, and the model, first transformation, and second transformation are stored in a memory associated with the metrology tool.


A system that can be used for used for semiconductor height inspection and metrology includes a complementary plate that is used with a beam splitter to create desired astigmatism and to remove chromatic aberration. Simultaneous optimization of lateral resolution and sensitivity can be enabled. The complementary plate can be made of the same material and have the same thickness as the beam splitter.


Patent
KLA Tencor | Date: 2016-11-07

A rotatable compensator configured to transmit non-collimated light over a broad range of wavelengths, including ultraviolet, with a high degree of retardation uniformity across the aperture is presented. In one embodiment, a rotatable compensator includes a stack of four individual plates in optical contact. The two thin plates in the middle of the stack are made from a birefringent material and are arranged to form a compound, zeroth order bi-plate. The remaining two plates are relatively thick and are made from an optically isotropic material. These plates are disposed on either end of the compound, zeroth order bi-plate. The low order plates minimize the sensitivity of retardation across the aperture to non-collimated light. Materials are selected to ensure transmission of ultraviolet light. The optically isotropic end plates minimize coherence effects induced at the optical interfaces of the thin plates.


A system includes a first beam splitter, a second beam splitter, and a mirror. The second beam splitter can produce two lines of light, which are received by at least one sensor. The two lines of light have different focal heights on the wafer. A distance between the second beam splitter and the mirror can be configured to change a focal height on the wafer. A height of an illuminated region on a surface of the wafer relative to a normal surface of the wafer can be determined using the two lines of light.


Patent
KLA Tencor | Date: 2016-01-08

Methods and systems for classifying defects detected on a specimen with an adaptive automatic defect classifier are provided. One method includes creating a defect classifier based on classifications received from a user for different groups of defects in first lot results and a training set of defects that includes all the defects in the first lot results. The first and additional lot results are combined to create cumulative lot results. Defects in the cumulative lot results are classified with the created defect classifier. If any of the defects are classified with a confidence below a threshold, the defect classifier is modified based on a modified training set that includes the low confidence classified defects and classifications for these defects received from a user. The modified defect classifier is then used to classify defects in additional cumulative lot results.


A method and system to measure misalignment error between two overlying or interlaced periodic structures are proposed. The overlying or interlaced periodic structures are illuminated by incident radiation, and the diffracted radiation of the incident radiation by the overlying or interlaced periodic structures are detected to provide an output signal. The misalignment between the overlying or interlaced periodic structures may then be determined from the output signal.


A repetition rate (pulse) multiplier includes one or more beam splitters and prisms forming one or more ring cavities with different optical path lengths that delay parts of the energy of each pulse. A series of input laser pulses circulate in the ring cavities and part of the energy of each pulse leaves the system after traversing the shorter cavity path, while another part of the energy leaves the system after traversing the longer cavity path, and/or a combination of both cavity paths. By proper choice of the ring cavity optical path length, the repetition rate of an output series of laser pulses can be made to be a multiple of the input repetition rate. The relative energies of the output pulses can be controlled by choosing the transmission and reflection coefficients of the beam splitters. Some embodiments generate a time-averaged output beam profile that is substantially flat in one dimension.


Grant
Agency: European Commission | Branch: H2020 | Program: ECSEL-IA | Phase: ECSEL-02-2014 | Award Amount: 139.30M | Year: 2015

The proposed pilot line project WAYTOGO FAST objective is to leverage Europe leadership in Fully Depleted Silicon on Insulator technology (FDSOI) so as to compete in leading edge technology at node 14nm and beyond preparing as well the following node transistor architecture. Europe is at the root of this breakthrough technology in More Moore law. The project aims at establishing a distributed pilot line between 2 companies: - Soitec for the fabrication of advanced engineered substrates (UTBB: Ultra Thin Body and BOx (buried oxide)) without and with strained silicon top film. - STMicroelectronics for the development and industrialization of state of the art FDSOI technology platform at 14nm and beyond with an industry competitive Power-Performance-Area-Cost (PPAC) trade-off. The project represents the first phase of a 2 phase program aiming at establishing a 10nm FDSOI technology for 2018-19. A strong added value network is created across this project to enhance a competitive European value chain on a European breakthrough and prepare next big wave of electronic devices. The consortium gathers a large group of partners: academics/institutes, equipment and substrate providers, semiconductor companies, a foundry, EDA providers, IP providers, fabless design houses, and a system manufacturer. E&M will contribute to the objective of installing a pilot line capable of manufacturing both advanced SOI substrates and FDSOI CMOS integrated circuits at 14nm and beyond. Design houses and electronics system manufacturer will provide demonstrator and enabling IP, to spread the FDSOI technology and establish it as a standard in term of leading edge energy efficient CMOS technology for a wide range of applications battery operated (consumer , healthcare, Internet of things) or not. Close collaboration between the design activities and the technology definition will tailor the PPAC trade-off of the next generation of technology to the applications needs.


Grant
Agency: European Commission | Branch: H2020 | Program: ECSEL-IA | Phase: ECSEL-15-2015 | Award Amount: 150.05M | Year: 2016

The TAKE5 project is the next in a chain of thematically connected ENIAC JU KET pilot line projects which are associated with 450mm/300mm development for the 10nm technology node and the ECSEL JU project SeNaTe aiming at the 7nm technology node. The main objective of the TAKE5 project is the demonstration of 5nm patterning in line with the industry needs and the ITRS roadmap in the Advanced Patterning Center at the imec pilot line using innovative design and technology co-optimization, layout and device architecture exploration, and comprising demonstration of a lithographic platform for EUV technology, advanced process and holistic metrology platforms and new materials. A lithography scanner will be developed based on EUV technology to achieve the 5nm module patterning specification. Metrology platforms need to be qualified for 5nm patterning of 1D, 2D and 3D geometries with the appropriate precision and accuracy. For the 5nm technology modules new materials will need to be introduced. Introduction of these new materials brings challenges for all involved deposition processes and the related equipment set. Next to new deposition processes also the interaction of the involved materials with subsequent etch steps will be studied. The project will be dedicated to find the best options for patterning. The project relates to the ECSEL work program topic Process technologies More Moore. It addresses and targets as set out in the MASP at the discovery of new Semiconductor Process, Equipment and Materials solutions for advanced CMOS processes that enable the nano-structuring of electronic devices with 5nm resolution in high-volume manufacturing and fast prototyping. The project touches the core of the continuation of Moores law which has celebrated its 50th anniversary and covers all aspects of 5nm patterning development.


Grant
Agency: European Commission | Branch: H2020 | Program: ECSEL-IA | Phase: ECSEL-02-2014 | Award Amount: 181.08M | Year: 2015

The SeNaTe project is the next in a chain of thematically connected ENIAC JU KET pilot line projects which are associated with 450mm/300mm development for the 12nm and 10nm technology nodes. The main objective is the demonstration of the 7nm IC technology integration in line with the industry needs and the ITRS roadmap on real devices in the Advanced Patterning Center at imec using innovative device architecture and comprising demonstration of a lithographic platform for EUV and immersion technology, advanced process and holistic metrology platforms, new materials and mask infrastructure. A lithography scanner will be developed based on EUV technology to achieve the 7nm module patterning specification. Metrology platforms need to be qualified for N7s 1D, 2D and 3D geometries with the appropriate precision and accuracy. For the 7nm technology modules a large number of new materials will need to be introduced. The introduction of these new materials brings challenges for all involved processes and the related equipment set. Next to new deposition processes also the interaction of the involved materials with subsequent etch, clean and planarization steps will be studied. Major European stakeholders in EUV mask development will collaboratively work together on a number of key remaining EUV mask issues. The first two years of the project will be dedicated to find the best options for patterning, device performance, and integration. In the last year a full N7 integration with electrical measurements will be performed to enable the validation of the 7nm process options for a High Volume Manufacturing. The SeNaTe project relates to the ECSEL work program topic Process technologies More Moore. It addresses and targets as set out in the MASP at the discovery of new Semiconductor Process, Equipment and Materials solutions for advanced CMOS processes that enable the nano-structuring of electronic devices with 7nm resolution in high-volume manufacturing and fast prototyping.

Loading KLA Tencor collaborators
Loading KLA Tencor collaborators