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Patent
KINSUS INTERCONNECT TECHNOLOGY Corporation | Date: 2013-11-20

An insulation layer structure includes an insulation layer, at least one glass fiber embedded in the insulation layer and at least one opening penetrating through the insulation layer and cutting off the glass fiber. The glass fiber projects from a sidewall of the opening such that the ratio of the length of the glass fiber projecting from the sidewall to the width of the opening is 0.233%. With the glass fiber projecting from the sidewall of the opening, the sidewall of the opening has large surface roughness and the surface area to contact with the electrolyte. As a result, the crystal growth rate for the electrolyte onto the sidewall is accelerated. Therefore, the adhesion between the electroplating layer and the sidewall of the opening is increased, thereby improving the reliability and the yield rate of the product.


Patent
KINSUS INTERCONNECT TECHNOLOGY Corporation | Date: 2013-03-29

Disclosed is a method of packaging a chip and a substrate, including the steps of forming a substrate with a thickness ranging from 70 to 150 m, which comprises a dielectric layer, a circuit metal layer stacked on the dielectric layer and bonding pads higher than the dielectric layer by 10 to 15 m; forming a stabilizing structure around the substrate to provide a receiving space; disposing the chip on the receiving space and bonding the pins of the chip with the bonding pads; and filling up the receiving space under the chip with a filling material to a total thickness ranging from 300 to 850 m. Without the plastic molding process, the present invention reduces the cost and the total thickness, and further prevents the substrate from warping by use of the stabilizing fixing structure.


Patent
KINSUS INTERCONNECT TECHNOLOGY Corporation | Date: 2013-08-06

A thin package structure with enhanced strength includes a support carrier plate and a thin circuit board. The thin circuit board is formed on the support carrier plate and includes a first circuit layer, a dielectric layer and a second circuit layer. The first circuit layer includes the first circuit patterns and the first connection pads. The dielectric layer covers the first circuit layer. The second circuit layer is formed on or embedded in an upper surface of the dielectric layer and includes the second circuit patterns and the second connection pads. Connection plugs are formed in the dielectric layer to connect the first and second connection pads. The support carrier plate provides mechanical strength to avoid warping or deforming. It is feasible to direct test the package structure without disassembling so as to improve the convenience in testing.


Patent
KINSUS INTERCONNECT TECHNOLOGY Corporation | Date: 2014-09-16

A method for manufacturing circuit board includes steps of forming upper and lower copper foil layers on upper and lower surface of a PI substrate, respectively, etching the upper and lower copper foil layers to form first and second electrical circuits, attaching first and second PI coverlays to the upper and lower copper foil layers, respectively, etching the PI substrate through a PI etching process to form at least one opening exposing the lower copper foil layer, and performing a surface treatment to form a solder layer electrically connected to the electrical circuit of the lower copper foil layer for soldering electrical elements in a subsequent process. Therefore, the circuit board with double side circuit and single side assembly is obtained. The present invention do not employ the process of exposure ink, thereby simplifying the whole manufacturing procedure and greatly improving preciseness of the circuit board.


Patent
KINSUS INTERCONNECT TECHNOLOGY Corporation | Date: 2014-06-04

A management system includes a product specification data base for storing a plurality of product numbers and product specifications corresponding to the product numbers respectively; a parameter-setting data base for storing principles of parameter-settings; a device specification data base for storing application rules for a plurality of process devices; an execution processor coupled to the product specification data base, the parameter-setting data base and the device specification data base for processing based on the product specification data base, the parameter-setting data base and the device specification data base to produce process recipes of products corresponding to the specification numbers and converting into a plurality of process files adapted to be applied by corresponding process devices; and a process recipe data base coupled to the execution processor for storing the plurality of process files.

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