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Bernasconi R.,Polytechnic of Milan | Molazemhosseini A.,Polytechnic of Milan | Cervati M.,Polytechnic of Milan | Armini S.,Kapeldreef 75 | Magagnin L.,Polytechnic of Milan
Journal of Electronic Materials | Year: 2016

All-wet electroless metallization of through-silicon vias (TSVs) with a width of 5 μm and a 1:10 aspect ratio was carried out. Immersion in a n-(2-aminoethyl) 3-aminopropyl-trimethoxysilane (AEAPTMS) self-assembled monolayer (SAM) was used to enhance the adhesion between the metal film and substrate. Contact angle variation and atomic force microscopy were used to verify the formation of a SAM layer. A PdCl2 solution was later used to activate the silanized substrates, exploiting the affinity of the –NH3 functional group of AEAPTMS to palladium. A nickel-phosphorus-boron electroless bath was employed to deposit the first barrier layer onto silicon. The NiPB growth rate was evaluated on flat silicon wafers, while the structure of the coating obtained was investigated via glow discharge optical emission spectroscopy. Cross-sectional scanning electron microscope observations were carried out on metallized TSVs to characterize the NiPB seed, the Cu seed layer deposited with a second electroless step, and the Cu superfilling obtained with a commercial solution. Complete filling of TSV was achieved. © 2016 The Minerals, Metals & Materials Society


Adelmann C.,Kapeldreef 75 | Pierreux D.,Kapeldreef 75 | Swerts J.,Kapeldreef 75 | Dewulf D.,Hasselt University | And 14 more authors.
Chemical Vapor Deposition | Year: 2010

For future generations of non-volatile memory applications, the replacement of the interpoly dielectric by a suitable high-k material is required. Rare-earth aluminates are potential candidates because they are predicted to combine a high dielectric permittivity with a large band gap. We demonstrate the atomic layer deposition (ALD) of GdxAl2-xO3 layers using Gd(iPrCp)3, trimethyl-aluminum (TMA), and H2O or O3. Process windows for both H2O and O3 as oxidants are explored. H2O is shown to lead to better GdxAl2-xO3 film properties than O3, although the accessible composition range is limited because of the hygroscopic nature of Gd2O3.


Su J.,Veeco MOCVD Operations | Posthuma N.,Kapeldreef 75 | Wellekens D.,Kapeldreef 75 | Saripalli Y.N.,Kapeldreef 75 | And 3 more authors.
Journal of Electronic Materials | Year: 2016

We are reporting the growth of AlGaN based enhancement-mode high electron mobility transistors (HEMTs) on 200 mm silicon (111) substrates using a single wafer metalorganic chemical vapor deposition reactor. It is found that TMAl pre-dosing conditions are critical in controlling the structural quality, surface morphology, and wafer bow of the HEMT stack. Optimal structural quality and pit-free surface are demonstrated for AlGaN HEMTs with pre-dosing temperature at 750°C. Intrinsically, carbon-doped AlGaN, is used as the current blocking layer in the HEMT structures. The lateral buffer breakdown and device breakdown characteristics, reach 400 V at a leakage current of 1 μA/mm measured at 150°C. The fabricated HEMT devices, with a Mg doped p-GaN gate layer, are operating in enhancement mode reaching a positive threshold voltage of 2–2.5 V, a low on-resistance of 10.5 Ω mm with a high drain saturation current of ~0.35 A/mm, and a low forward bias gate leakage current of 0.5 × 10−6 A/mm (Vgs = 7 V). Tight distribution of device parameters across the 200 mm wafers and over repeat process runs is observed. © 2016 The Minerals, Metals & Materials Society


Mitra S.,Kapeldreef 75 | Putzeys J.,Kapeldreef 75 | Lopez C.M.,Kapeldreef 75 | Pennartz C.M.A.,University of Amsterdam | Yazicioglu R.F.,Kapeldreef 75
Analog Integrated Circuits and Signal Processing | Year: 2015

A complete light weight 24 channel wireless neural recording system enabled by a custom IC is presented. By transmitting only the action potential (AP) data, the system power consumption is scaled based on the activity of the neural signal. By detecting an AP event prior to digitization, the ASIC can reduce the power consumed in all subsequent stages and yet conserves the entire AP shape without affecting the classification performance. The complete 2.5 cm3 head stage weighing below 7 g can operate for 3 h. The ASIC achieves <3.5 µVrms noise (both in AP and LFP band) and >70 dB CMRR. © 2015, Springer Science+Business Media New York.


Noia B.,Duke University | Chakrabarty K.,Duke University | Marinissen E.J.,Kapeldreef 75
Journal of Electronic Testing: Theory and Applications (JETTA) | Year: 2012

Testing of three-dimensional (3D) stacked ICs (SICs) is starting to receive considerable attention in the semiconductor industry. Since the die-stacking steps of thinning, alignment, and bonding can introduce defects, there may be a need to test multiple subsequent partial stacks during 3D assembly. We address the problem of test-architecture optimization for 3D stacked ICs to minimize overall test time when either the complete stack only, or the complete stack and multiple partial stacks, need to be tested. A general solution to this problem provides several options for 3D stack testing in a unified framework. We show that optimal test-architecture solutions and test schedules for multiple test insertions are different from their counterparts for a single final stack test. In addition, we present optimization techniques for the testing of TSVs and die-external logic in combination with the dies in the stack. © 2011 Springer Science+Business Media, LLC.


Khan S.,Technical University of Delft | Hamdioui S.,Technical University of Delft | Kukner H.,Kapeldreef 75 | Raghavan P.,Kapeldreef 75 | Catthoor F.,Kapeldreef 75
Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems | Year: 2012

As semiconductor manufacturing has entered into the nanoscale era, Bias Temperature Instability (BTI) became a major threat to reliability of CMOS circuits. This threat may even be more severe in the presence of parameter variations such as temperature and process. This paper presents simulation based analysis of BTI and parameter variations in logic gates. Delay, static and dynamic power consumptions are the metrics considered in the analysis. The simulation results show that while considering BTI only, the impact on delay is strongly temperature and duty cycle dependent. For example, in a NOR gate the delay at 75°C and 50% duty cycle is 56% higher than at 25°C; and at 40% duty cycle is 67% higher than at 60%. The results also show that BTI reduced the static and dynamic power. The analysis is redone for BTI by incorporating parameter variation. Monte Carlo simulation results reveal that BTI impact is exacerbated in the presence of parameter variations with up to 15%. © 2012 IEEE.


Khan S.,Technical University of Delft | Hamdioui S.,Technical University of Delft | Kukner H.,Kapeldreef 75 | Raghavan P.,Kapeldreef 75 | Catthoor F.,Kapeldreef 75
Proceedings - 2013 18th IEEE European Test Symposium, ETS 2013 | Year: 2013

In nanoscale era, Negative Bias Temperature Instability (NBTI) and Positive Bias Temperature Instability (PBTI) weaken PMOS and NMOS transistors, respectively, leading to performance degradation. This paper presents a comprehensive analysis of NBTI and PBTI impacts on SRAM decoders including single stage static and dynamic as well as two stage static decoders while applying realistic addressing schemes (i.e. linear, gray and address complement) to present different workloads. The analysis shows that the strength of the impact strongly depends on the decoder design and the addressing scheme; the impact can be as worst as 28% additional delay in the activation of the wordline. © 2013 IEEE.


Khan S.,Technical University of Delft | Hamdioui S.,Technical University of Delft | Kukner H.,Kapeldreef 75 | Raghavan P.,Kapeldreef 75 | Catthoor F.,Kapeldreef 75
Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2012 | Year: 2012

As semiconductor manufacturing has entered into the nanoscale era, Bias Temperature Instability (BTI) -Negative BTI (NBTI) in PMOS transistors and Positive BTI (PBTI) in NMOS transistors- has become one of the most serious aging mechanisms that reduces reliability of logic gates. This paper presents a simulation-based BTI analysis in both basic (such as NAND and NOR) and complex gates while considering the impact of input's duty cycle, the frequency at which they change, as well as the impact of the stressed transistor location. The simulation results show that the impact of BTI is strongly gate dependent and that in general the impact in complex gates is larger. When considering both NBTI and PBTI for basic gates, the results reveal that for a NOR gate the impact of NBTI is 2.19× higher than that of PBTI; while for a NAND gate, PBTI impact is 1.27× higher than that of NBTI. When considering different input duty cycles and their frequencies, the results show that the higher the duty cycle, the lower NBTI impact and the higher the PBTI impact regardless of the gate types and the frequency; a variation of ±30% duty cycle causes a variation of up to 49% variation in the impact of NBTI and a variation of 16% in the impact of PBTI. For complex gates, the results show similar trends, but with higher impact. © 2012 IEEE.


Procel L.M.,University of Calabria | Procel L.M.,San Francisco de Quito University | Crupi F.,University of Calabria | Trojman L.,San Francisco de Quito University | And 2 more authors.
IEEE Transactions on Device and Materials Reliability | Year: 2016

The defect-centric distribution is used to study the temperature dependence of channel hot carrier (CHC) degradation in deeply scaled nMOSFETs. We analyze the temperature dependence in terms of the defect-centric parameters. The total number of traps is observed to increase with temperature, whereas the average threshold voltage shift produced by a single charged defect, i.e., η, is confirmed to be independent of the temperature, as previously shown for bias temperature instability. By using the defect-centric analysis, we estimate the activation energy of the threshold voltage shift and that of the number of charged traps per device, which are directly linked to the CHC degradation. © 2015 IEEE.


Khan S.,Technical University of Delft | Taouil M.,Technical University of Delft | Hamdioui S.,Technical University of Delft | Kukner H.,Kapeldreef 75 | And 2 more authors.
2013 8th IEEE Design and Test Symposium, IDT 2013 | Year: 2013

Partial open defects in modern Static Random Access Memory (SRAM) address decoders are one of the main causes of small delays; these are hard to detect and may result in escapes and reliability problems. In addition, Aging failures - such as Bias Temperature Instability (BTI)-may worsen the situation and accelerate the degradation (i.e. increase the delay) and cause sooner field failures. This paper investigates the impact of partial opens and BTI in SRAM address decoders first separately and thereafter in a combined manner. Simulation results show that BTI impact strongly depends on the selected worldline, transistor location and addressing scheme; and it cause up to 14.27% additional delay. In addition, they show that partial opens, which do not cause hard faults and allow memory operations to pass correctly, contribute up to 23.65% additional delay. Combining these failure mechanisms reveals that the degradation can strongly be worsened and accelerate wear-out; an additional delay of up to 31.20% can be caused. This indicates the importance of incorporating appropriate design-for-reliability/testability schemes in order to guarantee the required lifetime of the memory system. © 2013 IEEE.

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