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Leuven, Belgium

Bernasconi R.,Polytechnic of Milan | Molazemhosseini A.,Polytechnic of Milan | Cervati M.,Polytechnic of Milan | Armini S.,Kapeldreef 75 | Magagnin L.,Polytechnic of Milan
Journal of Electronic Materials | Year: 2016

All-wet electroless metallization of through-silicon vias (TSVs) with a width of 5 μm and a 1:10 aspect ratio was carried out. Immersion in a n-(2-aminoethyl) 3-aminopropyl-trimethoxysilane (AEAPTMS) self-assembled monolayer (SAM) was used to enhance the adhesion between the metal film and substrate. Contact angle variation and atomic force microscopy were used to verify the formation of a SAM layer. A PdCl2 solution was later used to activate the silanized substrates, exploiting the affinity of the –NH3 functional group of AEAPTMS to palladium. A nickel-phosphorus-boron electroless bath was employed to deposit the first barrier layer onto silicon. The NiPB growth rate was evaluated on flat silicon wafers, while the structure of the coating obtained was investigated via glow discharge optical emission spectroscopy. Cross-sectional scanning electron microscope observations were carried out on metallized TSVs to characterize the NiPB seed, the Cu seed layer deposited with a second electroless step, and the Cu superfilling obtained with a commercial solution. Complete filling of TSV was achieved. © 2016 The Minerals, Metals & Materials Society Source


Noia B.,Duke University | Chakrabarty K.,Duke University | Marinissen E.J.,Kapeldreef 75
Journal of Electronic Testing: Theory and Applications (JETTA) | Year: 2012

Testing of three-dimensional (3D) stacked ICs (SICs) is starting to receive considerable attention in the semiconductor industry. Since the die-stacking steps of thinning, alignment, and bonding can introduce defects, there may be a need to test multiple subsequent partial stacks during 3D assembly. We address the problem of test-architecture optimization for 3D stacked ICs to minimize overall test time when either the complete stack only, or the complete stack and multiple partial stacks, need to be tested. A general solution to this problem provides several options for 3D stack testing in a unified framework. We show that optimal test-architecture solutions and test schedules for multiple test insertions are different from their counterparts for a single final stack test. In addition, we present optimization techniques for the testing of TSVs and die-external logic in combination with the dies in the stack. © 2011 Springer Science+Business Media, LLC. Source


Procel L.M.,University of Calabria | Procel L.M.,San Francisco de Quito University | Crupi F.,University of Calabria | Trojman L.,San Francisco de Quito University | And 2 more authors.
IEEE Transactions on Device and Materials Reliability | Year: 2016

The defect-centric distribution is used to study the temperature dependence of channel hot carrier (CHC) degradation in deeply scaled nMOSFETs. We analyze the temperature dependence in terms of the defect-centric parameters. The total number of traps is observed to increase with temperature, whereas the average threshold voltage shift produced by a single charged defect, i.e., η, is confirmed to be independent of the temperature, as previously shown for bias temperature instability. By using the defect-centric analysis, we estimate the activation energy of the threshold voltage shift and that of the number of charged traps per device, which are directly linked to the CHC degradation. © 2015 IEEE. Source


Khan S.,Technical University of Delft | Hamdioui S.,Technical University of Delft | Kukner H.,Kapeldreef 75 | Raghavan P.,Kapeldreef 75 | Catthoor F.,Kapeldreef 75
Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems | Year: 2012

As semiconductor manufacturing has entered into the nanoscale era, Bias Temperature Instability (BTI) became a major threat to reliability of CMOS circuits. This threat may even be more severe in the presence of parameter variations such as temperature and process. This paper presents simulation based analysis of BTI and parameter variations in logic gates. Delay, static and dynamic power consumptions are the metrics considered in the analysis. The simulation results show that while considering BTI only, the impact on delay is strongly temperature and duty cycle dependent. For example, in a NOR gate the delay at 75°C and 50% duty cycle is 56% higher than at 25°C; and at 40% duty cycle is 67% higher than at 60%. The results also show that BTI reduced the static and dynamic power. The analysis is redone for BTI by incorporating parameter variation. Monte Carlo simulation results reveal that BTI impact is exacerbated in the presence of parameter variations with up to 15%. © 2012 IEEE. Source


Khan S.,Technical University of Delft | Hamdioui S.,Technical University of Delft | Kukner H.,Kapeldreef 75 | Raghavan P.,Kapeldreef 75 | Catthoor F.,Kapeldreef 75
Proceedings - 2013 18th IEEE European Test Symposium, ETS 2013 | Year: 2013

In nanoscale era, Negative Bias Temperature Instability (NBTI) and Positive Bias Temperature Instability (PBTI) weaken PMOS and NMOS transistors, respectively, leading to performance degradation. This paper presents a comprehensive analysis of NBTI and PBTI impacts on SRAM decoders including single stage static and dynamic as well as two stage static decoders while applying realistic addressing schemes (i.e. linear, gray and address complement) to present different workloads. The analysis shows that the strength of the impact strongly depends on the decoder design and the addressing scheme; the impact can be as worst as 28% additional delay in the activation of the wordline. © 2013 IEEE. Source

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