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Xiang Y.,CAS Institute of Microelectronics | Luo Y.B.,CAS Institute of Microelectronics | Luo Y.B.,Hangzhou Zhongke Microelectronics Co. | Zhou R.J.,CAS Institute of Microelectronics | And 2 more authors.
Applied Mechanics and Materials | Year: 2013

A 1.575GHz SiGe HBT(heterojunction bipolar transistor) low-noise-amplifier(LNA) optimized for Global Positioning System(GPS) L1-band applications was presented. The designed LNA employed a common-emitter topology with inductive emitter degeneration to simultaneously achieve low noise figure and input impedance matching. A resistor-bias-feed circuit with a feedback resistor was designed for the LNA input transistor to improve the gain compression and linearity performance. The LNA was fabricated in a commercial 0.18μm SiGe BiCMOS process. The LNA achieves a noise figure of 1.1dB, a power gain of 19dB, a input 1dB compression point(P1dB) of -13dBm and a output third-order intercept point(OIP3) of +17dBm at a current consumption of 3.6mA from a 2.8V supply. © (2013) Trans Tech Publications, Switzerland.

Xiang Y.,CAS Institute of Microelectronics | Zhou R.,CAS Institute of Microelectronics | Duan L.,CAS Institute of Microelectronics | Gan Y.,CAS Institute of Microelectronics | And 6 more authors.
Zhongnan Daxue Xuebao (Ziran Kexue Ban)/Journal of Central South University (Science and Technology) | Year: 2013

The design and implementation of a low noise amplifier (LNA) based on 0.18 μm SiGe BiCMOS process for the RF circuits in GPS receivers was presented. It uses a BiFET Cascode structure and achieves ultra low noise and considerable linearity simultaneously. The heterogenous bipolar transistor (HBT) input transistor provides very low noise and a cascode MOSFET enhances the linearity. With the use of this mixed approach, it is easier to realize the trade-off between gain, noise figure, linearity and power consumption than the conventional full-HBT or full-MOSFET structures. The LNA consumes total 3.7 mA current under 2.85 V supply voltage and results in a simulated noise figure(NF) of 0.9 dB, a power gain of 19 dB, a input 1 dB compression power(ICP1) of 0.065 mW.

Yanbin L.,CAS Institute of Microelectronics | Jian S.,CAS Institute of Microelectronics | Chengyan M.,CAS Institute of Microelectronics | Chengyan M.,Hangzhou Zhongke Microelectronics Co. | And 3 more authors.
Journal of Semiconductors | Year: 2014

A high linearity 1.575 GHz SiGe:HBT low noise amplifier (LNA) for global positioning system applications is described. The bipolar cascoded with an MOSFET LNA was fabricated in a commercial 0.18 μm SiGe BiCMOS process. A resistor bias feed circuit with a feedback resistor was designed for the LNA input transistor to improve its intermodulation and compression performance. The packaged chip tested on board has displayed a noise figure of 1.11 dB, a power gain of 18 dB, an output 1 dB compression point of +7.8 dBm and an input third-order intercept point of +1.8 dBm. The chip occupies a 500 + 560 μm2 area and consumes 3.6 mA from a 2.85 V power supply. © 2014 Chinese Institute of Electronics.

Zhou R.,CAS Institute of Microelectronics | Ma C.,CAS Institute of Microelectronics | Ma C.,Hangzhou Zhongke Microelectronics Co. | Ma C.,Jiaxing Lianxing Microelectronics Co. | And 5 more authors.
Zhongnan Daxue Xuebao (Ziran Kexue Ban)/Journal of Central South University (Science and Technology) | Year: 2014

A low noise amplifier (LNA) for full-band global navigation satellite system (GNSS) receivers was presented. To improve the integration of the RF front end and cut down the costs, an implementation method based on emitter-Inductor degenerated wide-band LNA was proposed. Then the architecture, wide-band input impedance matching and noise performance were analyzed. Based on 0.18 µm SiGe BiCMOS technology, the LNA was designed and implemented. The results show that the minimum input and output return losses are 8.0 dB and 8.9 dB respectively, the maximum noise figure is 1.30 dB, a minimum power gain of 14.9 dB and an IIP3 of -5.8 dBm are achieved in GNSS full-band from 1 164 MHz to 1 610 MHz. The minimum power consumption is 9.6 mW and the die area is about 600 µm×650 µm.

Shi J.,CAS Institute of Microelectronics | Xiao S.,CAS Institute of Microelectronics | Yu Y.,CAS Institute of Microelectronics | Huang W.,CAS Institute of Microelectronics | And 5 more authors.
Proceedings - IEEE International Symposium on Circuits and Systems | Year: 2013

A fully integrated direct up-conversion transmitter for Chinese electronic toll collection system (ETCS) is presented in a 0.18um CMOS process. Improved isolation between power amplifier (PA) and voltage-control oscillator (VCO) is achieved by configuring the VCO frequency to be 2/3 transmission frequency. A 5.8GHz mixer with an automatic amplitude control (AAC) loop is proposed to obtain better amplitude shift keying (ASK) performance. The occupied bandwidth of the transmitter is optimized by digital filtering. A high-linearity ASK modulator translates the base-band signal to carrier frequency and a two-stage class-A and class-AB PA is adopted to obtain sufficient efficiency and relatively high linearity. The transmitter consumes only 99mW with 1.8V supply voltage to meet the low-power demand of Chinese ETCS and carries a single-ended 3.2dBm output power. Under 1.024Mbps data rate, the eye-opening is better than 91% and the transmitter achieves -58.2dBc adjacent channel power ratio (ACPR) and 1.46MHz occupied bandwidth. © 2013 IEEE.

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