Jiangyin Changdian Advanced Packaging Co.

Chengjiang, China

Jiangyin Changdian Advanced Packaging Co.

Chengjiang, China
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Gao L.-Y.,CAS Shenyang Institute of Metal Research | Liu Z.-Q.,CAS Shenyang Institute of Metal Research | Zhang L.,Jiangyin Changdian Advanced Packaging Co. | Guo H.,Jiangyin Changdian Advanced Packaging Co. | Lai C.-M.,Jiangyin Changdian Advanced Packaging Co.
2016 6th Electronic System-Integration Technology Conference, ESTC 2016 | Year: 2016

Fe-Ni film with compositions of 45wt.% Ni, which is also denoted as Fe-45Ni, was used as under bump metallization (UBM) to evaluate the interfacial reliability of SnAgCu/Fe-Ni solder joint under electromigration (EM) test. For comparison, commercial Cu UBM was also adopted in the reliability test. The microstructural evolutions of these two UBM solder joints were observed by scanning electron microscope (SEM). For SAC/Cu solder joints, the competition between the consumption of Cu cathode and the solder voiding led the ultimate failure, while the SAC/Fe-45Ni solder joints kept at a perfect condition without any signs of failure after 1000 hours EM test. The characteristic lifetime calculated by Weibull analysis for Fe-45Ni UBM was 2340 hours, which is three times longer than that of Cu UBM (698 hours), demonstrating an outstanding performance for Fe-45Ni UBM in electro-migration resistance. Accordingly, the superior EM resistance can be attributed to the reasons below. Firstly, Fe-45Ni UBM has an excellent barrier effect for Cu diffusion, due to the low diffusivity and high activation energy of interfacial intermetallic compounds (IMCs). Secondly, Fe flux originating from EM effect transports in the opposite direction to the diffusion flux under thermal effect at the cathode, thus it partly counteracted the diffusion flux and slow down the dissolution process of Fe-45Ni cathode. © 2016 IEEE.


Zhang H.,CAS Shenyang Institute of Metal Research | Zhu Q.-S.,CAS Shenyang Institute of Metal Research | Liu Z.-Q.,CAS Shenyang Institute of Metal Research | Zhang L.,Jiangyin Changdian Advanced Packaging Co. | And 2 more authors.
Journal of Materials Science and Technology | Year: 2014

Fe-Ni films with compositions of Fe-75Ni, Fe-50Ni, and Fe-30Ni were used as under bump metallization (UBM) to evaluate the interfacial reliability of SnAgCu/Fe-Ni solder joints through ball shear test, high temperature storage, and temperature cycling. The shear strengths for Fe-75Ni, Fe-50Ni, and Fe-30Ni solder joints after reflow were 42.57, 53.94 and 53.98 MPa, respectively, which were all satisfied the requirement of industrialization (>34.3 MPa). High temperature storage was conducted at 150, 175 and 200 °C. It was found that higher Fe content in Fe-Ni layer had the ability to inhibit the mutual diffusion at interface region below 150 °C, and the growth speed of intermetallic compound (IMC) decreased with increasing Fe concentration. When stored at 200 °C, the IMC thickness reached a limit for all three films after 4 days, and some cracks occurred at the interface between IMC and Fe-Ni layer. The activation energies for the growth of FeSn2 on Fe-30Ni, Fe-50Ni, and Fe-75Ni films were calculated as 246, 185, and 81 kJ/mol, respectively. Temperature cycling tests revealed that SnAgCu/Fe-50Ni solder joint had the lowest failure rate (less than 10%), and had the best interfacial reliability among three compositions. © 2014 .


Zhang H.,CAS Shenyang Institute of Metal Research | Wu D.,CAS Shenyang Institute of Metal Research | Zhang L.,Jiangyin Changdian Advanced Packaging Co. | Duan Z.,Jiangyin Changdian Advanced Packaging Co. | And 2 more authors.
Jinshu Xuebao/Acta Metallurgica Sinica | Year: 2012

Using customized wafer electroplating system, the electrodeposition process of Fe-Ni under bump metallization (UBM) thin film has been developed by modified Watts bath. The major factors which can affect the Fe content in the final UBM films, including the concentration of Fe2+, electrodeposition temperature and current density, were investigated systematically. The growth rate of Fe-Ni film under different electroplating conditions was measured in order to provide a reference for actual production. The microstructure and morphology of obtained Fe-Ni films were characterized by XRD and TEM. Multiple kinds of analytical methods including titration and inductive coupled plasma emission spectrometer (ICP) were used to monitor the content change of bath component under working or storage conditions. Regulations were put forward to maintain the bath daily including the keeping of the main salt content and the inhibition of Fe3+ concentration.


Chen D.,Jiangyin Changdian Advanced Packaging CO. | Zhang L.,Jiangyin Changdian Advanced Packaging CO. | Xie Y.,Jiangyin Changdian Advanced Packaging CO. | Tan K.,Jiangyin Changdian Advanced Packaging CO. | Lai C.,Jiangyin Changdian Advanced Packaging CO.
ICEPT-HDP 2012 Proceedings - 2012 13th International Conference on Electronic Packaging Technology and High Density Packaging | Year: 2012

LED (light-emitting diode) has many advantages over traditional lighting source such as higher electrical efficiency, faster response, and free of hazardous, which has been attracting more and more interesting from all of world. LED technology has achieved remarkable progress during latest years already. However, high price is still the main block for its wide application. © 2012 IEEE.


Yang D.,Fudan University | Ye X.,Fudan University | Xiao F.,Fudan University | Chen D.,Jiangyin Changdian Advanced Packaging Co. | Zhang L.,Jiangyin Changdian Advanced Packaging Co.
ICEPT-HDP 2012 Proceedings - 2012 13th International Conference on Electronic Packaging Technology and High Density Packaging | Year: 2012

Wafer level packaging (WLP) is regarded as one of the most potential single chip packages for its compatibility with wafer fabrication process. As the pitch size of the package becomes lower, the reliability of fine pitch WLP devices is greatly challenged. Finer pitch may result in weaker solder joints, which leads to reliability problems such as fatigue failure, creep deformation and so on. Much work has been done to investigate the reliability of wafer level package above 500 μm pitch under different conditions such as temperature cycling, thermal shock and drop test, etc. Nevertheless, there are few reports about the reliability of WLP with pitch size less than 500 μm. In this study, WLP with a size of 5×5 mm2 and a pitch of 400 μm were fabricated. Each chip has 144 lead-free SAC105 solder balls in an array of 12×12. The chips are reflowed on Ni/Au pads on boards. The chips were experienced a set of reliability tests including temperature cycling, thermal shock and drop test according to JEDEC standards. Furthermore, failure analysis is carried out to study the failure mechanism. Failures are found mostly inside of the solder ball after TC and TS tests, while the drop tests cause more damage to the solder-board and solder-chip interface. © 2012 IEEE.


Bian X.,Jiangyin Changdian Advanced Packaging Co. | Guo H.,Jiangyin Changdian Advanced Packaging Co. | Zhang L.,Jiangyin Changdian Advanced Packaging Co. | Tan K.,Jiangyin Changdian Advanced Packaging Co. | Lai C.,Jiangyin Changdian Advanced Packaging Co.
ICEPT-HDP 2012 Proceedings - 2012 13th International Conference on Electronic Packaging Technology and High Density Packaging | Year: 2012

With the development of radio frequency wireless communication technology, there are strong demands of spiral inductor with high performance and low profile. The inductor is a basic component of IPD (Integrated Passive Devices [1]) including oscillators, filters, mixers and baluns. In this paper, the structure and process of fabricating a high performance wafer level silicon-base spiral inductor was presented and the effects of geometrical parameters on the inductance and quality factor were studied via a commercial 3-D EM [2] (Electromagnetic) simulator software. The performance was compared with the traditional on-chip embedded inductors. The results show that the number of turns and inner radius significantly impact the inductance and the performance of the mentioned spiral inductor is better than the traditional on-chip embedded inductors. © 2012 IEEE.


Xie Y.,Jiangyin Changdian Advanced Packaging CO. | Chen D.,Jiangyin Changdian Advanced Packaging CO. | Zhang L.,Jiangyin Changdian Advanced Packaging CO. | Tan K.H.,Jiangyin Changdian Advanced Packaging CO. | Lai C.M.,Jiangyin Changdian Advanced Packaging CO.
Proceedings - 2013 14th International Conference on Electronic Packaging Technology, ICEPT 2013 | Year: 2013

After the first white light-emitting diodes (WLEDs) became commercially available, much attention has been paid to the development of WLEDs because of their extensive applications in solid lighting. Compared with traditional lighting, WLEDs have more advantages, such as high efficiency, long lifetime, fast response and environmental-friendliness [1-3]. It has been widely used in signals, displays and lighting. However, high price is still the main block for its wide application. As a new LED packaging solution, wafer level packaging(WLP) has attracted more and more interesting for whole semiconductor industry for predictable advantages over traditional packaging types, WLP is an as-know low cost packaging method, which has been demonstrated in IC (integrated circuit) industry already [4-5]. In this paper, a novel packaging for white LED, benefit from Si material and TSV array used in the wafer level LED package, the capability of thermal dissipation could be enhanced. Compared to the traditional LED, there are many advantages of this package, The advantages of this 3D integration package are:(1) good thermal diffusivity, (2) good light efficiency, (3) less footprint. The structure of the packaged LED was characterized, and light performance was tested according to standard LED testing method, and thermal resistance was simulated and tested, the result is close to Cree LED. © 2013 IEEE.


Patent
Jiangyin Changdian Advanced Packaging Co. | Date: 2013-12-26

An LED packaging structure comprises a silicon-based body and an LED chip. Discontinuous metal reflective layers are disposed on the obverse surface of the silicon-based body. A metal layer I and a metal layer II that are discontinuous are disposed in a silicon through hole. An LED chip electrode, a metal block/post, the metal reflective layer and the metal layer I are electrically connected. An LED chip electrode, a metal block/post, the metal reflective layer and the metal layer II are electrically connected. A metal layer III is located on a surface of an insulation layer II at the back of the silicon-based body and is located between the metal layer I and the metal layer II. According to the packaging structure, the LED packaging structure with omnidirectional light emission is obtained by means of a wafer level packaging technology; the LED packaging structure can reduce the thermal resistance, improve the reliability, enable the light emission angle not to be limited, and reduce design and manufacturing costs.


Patent
Jiangyin Changdian Advanced Packaging Co. | Date: 2011-10-21

A low-k chip packaging structure comprising chip body I (2-1), a chip electrode (2-2), and a chip surface passivation layer (2-3). Chip body I (2-1) has coated thereon thin film layer I (2-3). Thin film layer I (2-3) has arranged on a rear face thereof a support wafer (2-5). A chip electrode (2-2) is transferred to thin film layer I (2-4) around the exterior of the chip via a rewired metal wiring (2-6). The rewired metal wiring (2-6) has arranged at an end thereof a metal column (2-7). The metal column (2-7) has coated thereon thin film layer II (2-8). The top of the metal column protrudes thin film layer II (2-8). The protruding top of the metal column (2-7) has arranged thereon a metal layer (2-9). The metal layer (2-9) has arranged thereon soldering balls (2-10). The low-k chip packaging structure solves the problem of invalid low-k chip due to concentration of stress during chip packaging process and allows for reduced packaging costs and great product reliability.


Patent
Jiangyin Changdian Advanced Packaging Co. | Date: 2011-10-21

Provided is a method for packaging a low-k chip, comprising: attaching onto a carrier wafer a layer of temporary strippable film; arranging inversely a chip (2-1) onto the carrier wafer via the temporary strippable film; attaching thin film layer I (2-4) onto the carrier wafer for packaging; bonding a support wafer (2-5) onto the thin film layer I (2-4) and solidifying; forming a reconstructed wafer consisting of the chip (2-1), thin film layer I (2-4), and the support wafer; detaching the reconstructed wafer from the carrier wafer; completing a rewired metal wiring (2-6) on thin film layer I (2-4); forming a metal column (2-7) at an end of the rewired metal wiring (2-6); attaching thin film layer II (2-8) onto a surface of the metal column (2-7), packaging, and solidifying; coating a metal layer (2-9) on the top of the metal column (2-7), forming BGA solder balls (2-10) on the metal layer (2-9) by means of printing or ball planting; and finally slicing into individual BGA packages the reconstructed wafer having formed the BGA solder balls (2-10).

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