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Ma C.,Nanjing Southeast University | Xu P.,Nanjing Southeast University | Xu P.,Jiangsu Provincial Key Laboratory of Sensor Network Technology
Proceedings of the 2013 6th International Congress on Image and Signal Processing, CISP 2013

For face recognition, we consider the problem of automatically recognizing human faces from frontal views with varying facial expression and illumination circumstance, as well as noise. In this paper, a new algorithm is proposed, which avoids the crucial issue of feature extraction in conventional face recognition. Firstly, we use the gradient projection method to improve the performance of sparse representation classification (SRC). And then, a new algorithm dubbed classified gradient projection for sparse representation (CGPSR) is proposed, which utilizes the classification information to enhance the performance for recognizing images with noise. Simulation results demonstrate that the proposed CGPSR algorithm outperforms the previously proposed SRC-based orthogonal matching pursuit (OMP) and has a good potential in the robustness to noise. © 2013 IEEE. Source

Li Z.-Q.,Nanjing Southeast University | Li Z.-Q.,Jiangsu Provincial Key Laboratory of Sensor Network Technology | Zhao S.,Nanjing Southeast University
Jiefangjun Ligong Daxue Xuebao/Journal of PLA University of Science and Technology (Natural Science Edition)

A 0.5 V 4.8 GHz CMOS LC VCO for WSN application was designed. The VCO uses traditional differential negative-resistance structure. With a switched capacitor array, VCO achieves a large tuning range. Thanks to the combination of voltage-boosting circuit, VCO can have a control voltage larger than the supply voltage. Several technologies like width-length-ratio-adjusting of the transistors were used to optimize phase noise performance. The VCO uses 0.13 μm CMOS technology. The proposed VCO achieves a phase noise less than -115 dBc/Hz@1 MHz, and -121.2 dBc/Hz at most and consumes about 2.6 mA core current at 0.5 voltage supply. The performance of VCO meets the requirement of the design target. Source

Wang L.,Nanjing Southeast University | Wang L.,Jiangsu Provincial Key Laboratory of Sensor Network Technology | Li Z.,Nanjing Southeast University | Li Z.,Jiangsu Provincial Key Laboratory of Sensor Network Technology
Lecture Notes in Electrical Engineering

As the CMOS technology scaling into nanometer and the power supply voltage decrease, low-voltage circuit design becomes a challenge. A divider-by-2 with 0.5 V power supply implemented in TSMC 0.13 μm 1P8M CMOS process is designed to produce 2.4 ~ 2.5 GHz quad-signals for Wireless Sensor Networks (WSN). To reduce the threshold voltage of transistors, low-threshold (LT) NMOS transistor in Deep-N-Well (DNW) with Forward-Body Bias technique is used in the circuits. The design of layout with DNW and isolation of the bulk of the LT NMOS with the substrate are explained in this chapter. The post-simulated operating frequency range is 2.5 ~ 7 GHz and the power consumption is 0.9 mW at 5 GHz. © 2014 Springer Science+Business Media New York. Source

Zhao S.,Nanjing Southeast University | Li Z.,Nanjing Southeast University | Li Z.,Jiangsu Provincial Key Laboratory of Sensor Network Technology
2012 4th International High Speed Intelligent Communication Forum, HSIC 2012, Proceeding

A 1.8 GHz LC VCO in 1.8-V supply is presented. The VCO achieves low power consumption by optimum selection of inductance in the L-C tank. To increase the tuning range, a three-bit switching capacitor array is used for digital switched tuning. Designed in 0.18m RF CMOS technology, the proposed VCO achieves a phase noise of 126.2dBc/Hz at 1MHz offset and consumes 1.38mA core current at 1.8-V voltage supply. © 2012 IEEE. Source

Zhang M.,Nanjing Southeast University | Zhang M.,Jiangsu Provincial Key Laboratory of Sensor Network Technology | Li Z.,Nanjing Southeast University | Li Z.,Jiangsu Provincial Key Laboratory of Sensor Network Technology
Journal of Semiconductors

This paper presents a differential low power low noise amplifier designed for the wireless sensor network (WSN) in a TSMC 0.18 μm RF CMOS process. A two-stage cross-coupling cascaded common-gate (CG) topology has been designed as the amplifier. The first stage is a capacitive cross-coupling topology. It can reduce the power and noise simultaneously. The second stage is a positive feedback cross-coupling topology, used to set up a negative resistance to enhance the equivalent Q factor of the inductor at the load to improve the gain of the LNA. A differential inductor has been designed as the load to achieve reasonable gain. This inductor has been simulated by the means of momentum electromagnetic simulation in ADS. A "double-π" circuit model has been built as the inductor model by iteration in ADS. The inductor has been fabricated separately to verify the model. The LNA has been fabricated and measured. The LNA works well centered at 2.44 GHz. The measured gain S 21 is variable with high gain at 16.8 dB and low gain at 1 dB. The NF (noise figure) at high gain mode is 3.6 dB, the input referenced 1 dB compression point (IP1dB) is about -8 dBm and the IIP3 is 2 dBm at low gain mode. The LNA consumes about 1.2 mA current from 1.8 V power supply. © 2012 Chinese Institute of Electronics. Source

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