Jiangsu Provincial Key Laboratory of Sensor Network Technology

Wuxi, China

Jiangsu Provincial Key Laboratory of Sensor Network Technology

Wuxi, China
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Ma C.,Nanjing Southeast University | Xu P.,Nanjing Southeast University | Xu P.,Jiangsu Provincial Key Laboratory of Sensor Network Technology
Proceedings of the 2013 6th International Congress on Image and Signal Processing, CISP 2013 | Year: 2013

For face recognition, we consider the problem of automatically recognizing human faces from frontal views with varying facial expression and illumination circumstance, as well as noise. In this paper, a new algorithm is proposed, which avoids the crucial issue of feature extraction in conventional face recognition. Firstly, we use the gradient projection method to improve the performance of sparse representation classification (SRC). And then, a new algorithm dubbed classified gradient projection for sparse representation (CGPSR) is proposed, which utilizes the classification information to enhance the performance for recognizing images with noise. Simulation results demonstrate that the proposed CGPSR algorithm outperforms the previously proposed SRC-based orthogonal matching pursuit (OMP) and has a good potential in the robustness to noise. © 2013 IEEE.


Shen C.,Nanjing Southeast University | Shen C.,Jiangsu Provincial Key Laboratory of Sensor Network Technology | Li Z.,Nanjing Southeast University | Li Z.,Jiangsu Provincial Key Laboratory of Sensor Network Technology
IEEE MTT-S International Microwave Workshop Series on Millimeter Wave Wireless Technology and Applications, IMWS 2012 - Proceeding | Year: 2012

This paper shows a low power low-noise mixer in RFCMOS 0.18μm technology that operates between 0.3-3.8GHz. The low power mixer has a Gilbert cell configuration which employs low-noise transconductors designed using the noise-cancelling technique. And the low-noise amplifier designs use the current-reused topology to reduce power consumption and employ a capacitive cross-coupled (CCC) gm-boosting to improve noise performance. This merged front-end achieves 11-17dB power conversion gain, a flat SSB noise figure of 7.3-11dB with IF 2MHz over the whole working range. It only consumes 1.69mA current from a 1.8V supply and its active area occupies only 0.04mm 2. © 2012 IEEE.


Li Z.,Nanjing Southeast University | Li Z.,Jiangsu Provincial Key Laboratory of Sensor Network Technology | Wang Z.,Nanjing Southeast University | Wang Z.,Jiangsu Provincial Key Laboratory of Sensor Network Technology | And 6 more authors.
IEEE Microwave and Wireless Components Letters | Year: 2014

An ultra-low-power common-gate low noise amplifier (CG-LNA) for 2.4 GHz wireless sensor network (WSN) applications is proposed in this letter. The current-reuse and active gm-boosting techniques are utilized. The analysis, design method and measurement results are shown. An implemented prototype using 0.18 μm CMOS technology is evaluated using on-wafer probing. Measurements also show a gain of 14.7 dB and an IIP3 of 2 dBm at 2.44 GHz. The measured noise figure is 4.8 dB at 2.44 GHz. S11 is below-18 dB from 2-3 GHz. The proposed LNA consumes 0.58 mW from 1.8 V dc supply. © 2014 IEEE.


Wang L.,Nanjing Southeast University | Wang L.,Jiangsu Provincial Key Laboratory of Sensor Network Technology | Li Z.,Nanjing Southeast University | Li Z.,Jiangsu Provincial Key Laboratory of Sensor Network Technology
Lecture Notes in Electrical Engineering | Year: 2014

As the CMOS technology scaling into nanometer and the power supply voltage decrease, low-voltage circuit design becomes a challenge. A divider-by-2 with 0.5 V power supply implemented in TSMC 0.13 μm 1P8M CMOS process is designed to produce 2.4 ~ 2.5 GHz quad-signals for Wireless Sensor Networks (WSN). To reduce the threshold voltage of transistors, low-threshold (LT) NMOS transistor in Deep-N-Well (DNW) with Forward-Body Bias technique is used in the circuits. The design of layout with DNW and isolation of the bulk of the LT NMOS with the substrate are explained in this chapter. The post-simulated operating frequency range is 2.5 ~ 7 GHz and the power consumption is 0.9 mW at 5 GHz. © 2014 Springer Science+Business Media New York.


Zhang M.,Nanjing Southeast University | Zhang M.,Jiangsu Provincial Key Laboratory of Sensor Network Technology | Li Z.,Nanjing Southeast University | Li Z.,Jiangsu Provincial Key Laboratory of Sensor Network Technology
Journal of Semiconductors | Year: 2012

This paper presents a differential low power low noise amplifier designed for the wireless sensor network (WSN) in a TSMC 0.18 μm RF CMOS process. A two-stage cross-coupling cascaded common-gate (CG) topology has been designed as the amplifier. The first stage is a capacitive cross-coupling topology. It can reduce the power and noise simultaneously. The second stage is a positive feedback cross-coupling topology, used to set up a negative resistance to enhance the equivalent Q factor of the inductor at the load to improve the gain of the LNA. A differential inductor has been designed as the load to achieve reasonable gain. This inductor has been simulated by the means of momentum electromagnetic simulation in ADS. A "double-π" circuit model has been built as the inductor model by iteration in ADS. The inductor has been fabricated separately to verify the model. The LNA has been fabricated and measured. The LNA works well centered at 2.44 GHz. The measured gain S 21 is variable with high gain at 16.8 dB and low gain at 1 dB. The NF (noise figure) at high gain mode is 3.6 dB, the input referenced 1 dB compression point (IP1dB) is about -8 dBm and the IIP3 is 2 dBm at low gain mode. The LNA consumes about 1.2 mA current from 1.8 V power supply. © 2012 Chinese Institute of Electronics.


Yang T.,Nanjing Southeast University | Li Z.,Nanjing Southeast University | Li Z.,Jiangsu Provincial Key Laboratory of Sensor Network Technology
2012 4th International High Speed Intelligent Communication Forum, HSIC 2012, Proceeding | Year: 2012

A 7-bit 26MS/s SAR (successive approximation register) ADC is presented in this paper for the application of ZigBee receiver. Compared to the conventional method, the set-and-down method reduces the average switching energy by around 80%. Dynamic comparator is chosen to diminish the signal-dependent offset caused by the non-fixed input common-mode voltage. A prototype ADC was implemented in a CMOS 0.18-m technology. The ADC consumes 1.66 mW at 26MS/s under a 1.8-V supply. The post-simulation shows that SNDR and SFDR are 43.11dB and 57.49dB, when sampling 3.19921875 MHz sinusoid input signal at 26MHz sampling clock. © 2012 IEEE.


Xu H.,Nanjing Southeast University | Li Z.,Nanjing Southeast University | Li Z.,Jiangsu Provincial Key Laboratory of Sensor Network Technology
2012 4th International High Speed Intelligent Communication Forum, HSIC 2012, Proceeding | Year: 2012

In this paper, the design of a charge pump circuit suitable for lower power PLL-based frequency synthesizer is presented. The charge pump circuit was designed in 0.18m CMOS process. The proposed charge pump circuit improves current matching in a wide output voltage range by applying a wide input ranged operational amplifier. The percentage error of current mismatch for the output range from 0.3V to 1.7V is less than 0.005%. The power consumption of the proposed charge pump circuit is around 0.56mW at a supply voltage of 1.8V. © 2012 IEEE.


Zhao S.,Nanjing Southeast University | Li Z.,Nanjing Southeast University | Li Z.,Jiangsu Provincial Key Laboratory of Sensor Network Technology
2012 4th International High Speed Intelligent Communication Forum, HSIC 2012, Proceeding | Year: 2012

A 1.8 GHz LC VCO in 1.8-V supply is presented. The VCO achieves low power consumption by optimum selection of inductance in the L-C tank. To increase the tuning range, a three-bit switching capacitor array is used for digital switched tuning. Designed in 0.18m RF CMOS technology, the proposed VCO achieves a phase noise of 126.2dBc/Hz at 1MHz offset and consumes 1.38mA core current at 1.8-V voltage supply. © 2012 IEEE.


Chen L.,Nanjing Southeast University | Chen L.,Jiangsu Provincial Key Laboratory of Sensor Network Technology | Li Z.,Nanjing Southeast University | Li Z.,Jiangsu Provincial Key Laboratory of Sensor Network Technology
Journal of Semiconductors | Year: 2012

This paper presents a low noise amplifier (LNA), which could work at an ultra-low voltage of 0.5 V and was optimized for WSN application using 0.13 μm RF-CMOS technology. The circuit was analyzed and a new optimization method for a folded cascode LNA was introduced. Measured results of the proposed circuit demonstrated a power gain of 14.13 dB, consuming 3 mW DC power, showing 1.96 dB NF and an input 1-dB compression point of -19.9 dBm. Both input power matching (S 11) and output power matching (S 22) were below -10 dB. The results indicate that this LNA is fully applicable to low voltage and low power applications. © 2012 Chinese Institute of Electronics.


Wang Z.,Nanjing Southeast University | Wang Z.,Jiangsu Provincial Key Laboratory of Sensor Network Technology | Li Z.,Nanjing Southeast University | Li Z.,Jiangsu Provincial Key Laboratory of Sensor Network Technology
Conference Proceedings - 13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015 | Year: 2015

A low-voltage low-power CMOS ZigBee receiver front-end supporting 780/868/915/2400MHz bands is presented in this paper. The wideband common-gate (CG) low noise amplifier (LNA) and the I/Q current-commutating mixer are merged in a single circuit, sharing the bias current. Active trans-conductance (gm) boosting technique is utilized in the design of the presented receiver front-end. The topology and optimization method of the presented front-end are shown. Post-layout simulation results for 180nm RF CMOS implementations show the conversion gain is 26.5dB at 780/868/915MHz bands and 19.5dB at 2400MHz band. The minimum simulated NF is 6.5dB. The receiver front-end consumes 830μW from a 1V DC supply and the active size of core circuit is 0.0276mm2. © 2015 IEEE.

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