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Chen X.,Nanjing University of Posts and Telecommunications | Xu Y.,Nanjing University of Posts and Telecommunications | Xu Y.,Jiangsu Provincial Engineering Laboratory of RF Integration and Micropackaging | Xie X.,Nanjing University of Posts and Telecommunications | And 3 more authors.
China Semiconductor Technology International Conference 2015, CSTIC 2015 | Year: 2015

A novel Hall dynamic offset cancellation circuit based on four-phase spinning current technique is introduced. The offset cancellation circuit of Hall sensor applies a novel configuration including four-phase spinning current modulator, instrumentation amplifier, correlated double sampling demodulator and adder, which effectively eliminate the offset and 1/f noise, and linearly amplify the Hall signal. Designed in 0.8 μm high voltage CMOS technology, the circuit simulation results show the residual offset is lower than 0.2 mT and the linearity is up to 99.9%. © 2015 IEEE. Source


Xie X.,Nanjing University of Posts and Telecommunications | Xu Y.,Nanjing University of Posts and Telecommunications | Xu Y.,Jiangsu Provincial Engineering Laboratory of RF Integration and Micropackaging | Huang Y.,Nanjing University of Posts and Telecommunications | And 4 more authors.
China Semiconductor Technology International Conference 2015, CSTIC 2015 | Year: 2015

Presently TCAD simulation of single photon avalanche diode (SPAD) cannot directly obtain the important performances of SPAD. In this paper, we propose a new simulation method combining TCAD simulation with the numerical computation, which can exactly predict the statistical performances of SPAD such as Quantum Detection Efficiency (QDE), Dark Count Rate (DCR) and Afterpulsing Probability (AP). This new simulation method is useful in optimizing SPAD design with higher QDE and lower DCR. © 2015 IEEE. Source


Zhang Y.,Jiangsu Provincial Engineering Laboratory of RF Integration and Micropackaging | Zhang Y.,Nanjing University of Posts and Telecommunications | Meng Q.,Nanjing Southeast University | Wang D.,Jiangsu Provincial Engineering Laboratory of RF Integration and Micropackaging | And 5 more authors.
Progress in Electromagnetics Research Symposium | Year: 2015

A single channel 2 GSps, 8 bit folding and interpolation (F&I) analog-to-digital converter (ADC) designed in TSMC 90nm CMOS technology was presented in this paper. The ADC utilized cascaded folding architecture, which incorporated an additional inter-stage sample-and-hold amplifier between the two stages of folding circuits to enhance the quantization time. A pipelined track-and-hold amplifier (THA) with bootstrapped switch was taken as the front-end THA to improve its performance. The foreground digital assisted calibration was also employed in this design to correct the error of zero-crossing point caused by the circuit offset, thus to improve the linearity of the ADC. Chip area of the whole ADC including pads is 930 μm × 930μm. Post simulation results demonstrate that under a single supply of 1.2 Volts, the ADC consumes 210 mW. For the clock of 2GHz, the signal to noise and distortion ratio (SNDR) is 45.93dB for Nyquist input signal frequency. Source

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