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Raghogarh, India

Jaypee University of Engineering & Technology is a private engineering university located at Raghogarh, Guna, Madhya Pradesh, India. The university curriculum focuses on undergraduate and postgraduate engineering studies and research in engineering disciplines. Wikipedia.

Mohanty B.K.,Jaypee University of Engineering & Technology | Meher P.K.,Institute for Infocomm Research
IEEE Transactions on Signal Processing | Year: 2011

In this paper, we present a modular and pipeline architecture for lifting-based multilevel 2-D DWT, without using line-buffer and frame-buffer. Overall area-delay product is reduced in the proposed design by appropriate partitioning and scheduling of the computation of individual decomposition-levels. The processing for different levels is performed by a cascaded pipeline structure to maximize the hardware utilization efficiency (HUE). Moreover, the proposed structure is scalable for high-throughput and area-constrained implementation. We have removed all the redundancies resulting from decimated wavelet filtering to maximize the HUE. The proposed design involves L pyramid algorithm (PA) units and one recursive pyramid algorithm (RPA) unit, where R=N/P, L = ⌈ log4P⌉ and p is the input block size, M and N, respectively, being the height and width of the image. The entire multilevel DWT is computed by the proposed structure in MR cycles. The proposed structure has O(8R×2L) cycles of output latency, which is very small compared to the latency of the existing structures. Interestingly, the proposed structure does not require any line-buffer or frame-buffer, unlike the existing folded structures which otherwise require a line-buffer of size O(N) and frame-buffer of size O(M/2×N/2) for multilevel 2-D computation. Instead of those buffers, the proposed structure involves only local registers and RAM of size O(N). The saving of line-buffer and frame-buffer achieved by the proposed design is an important advantage, since the image size could very often be as large as 512 × 512. From the simulation results we find that, the proposed scalable structure offers better slice-delay-product (SDP) for higher throughput of implementation since the on-chip memory of this structure remains almost unchanged with input block size. It has 17% less SDP than the best of the corresponding existing structures on average, for different input-block sizes and image sizes. It involves 1.92 times more transistors, but offers 12.2 times higher throughput and consumes 52% less power per output (PPO) compared to the other, on average for different input sizes. © 2011 IEEE. Source

Mohanty B.K.,Jaypee University of Engineering & Technology
IEEE Transactions on Circuits and Systems I: Regular Papers | Year: 2015

A poly-phase based interpolation filter computation involves an input-matrix and coefficient-matrix of size (P × M) each, where P is the up-sampling factor and M=N/P, N is the filter length. The input-matrix and the coefficient-matrix resizes when P changes. An analysis of interpolation filter computation for different up-sampling factors is made in this paper to identify redundant computations and removed those by reusing partial results. Reuse of partial results eliminates the necessity of matrix resizing in interpolation filter computation. A novel block-formulation is presented to share the partial results for parallel computation of filter outputs of different up-sampling factors. Using the proposed block formulation, a parallel multiplier-based reconfigurable architecture is derived for interpolation filter. The most remarkable aspect of the proposed architecture is that, it does not require reconfiguration to compute filter outputs of an interpolation filter for different up-sampling factor. The proposed structure has regular data-flow and it has no overhead complexity for its reconfigurable feature unlike the existing structures. Besides, the proposed structure has significantly less register complexity than the existing structure and its register complexity is independent of the block-size. Moreover, the proposed structure can support higher input-sampling frequency than the existing structure. ASIC synthesis result shows that the proposed structure for block-size 4, filter length 32, and up-sampling factor 8, involves 13.6 times more area and offers 245 times higher maximum input-sampling frequency compared with the existing multiplier-less structure. It involves 18.6 times less area-delay-product (ADP) and 9.5 times less energy per output (EPO) than the existing multiplier-less structure. © 2014 IEEE. Source

Mohanty B.K.,Jaypee University of Engineering & Technology | Meher P.K.,Institute for Infocomm Research
IEEE Transactions on Signal Processing | Year: 2013

In this paper, we present an efficient distributed-arithmetic (DA) formulation for the implementation of block least mean square (BLMS) algorithm. The proposed DA-based design uses a novel look-up table (LUT)-sharing technique for the computation of filter outputs and weight-increment terms of BLMS algorithm. Besides, it offers significant saving of adders which constitute a major component of DA-based structures. Also, we have suggested a novel LUT-based weight updating scheme for BLMS algorithm, where only one set of LUTs out of $M$ sets need to be modified in every iteration, where $N=ML$ , $N$, and $L$ are, respectively, the filter length and input block-size. Based on the proposed DA formulation, we have derived a parallel architecture for the implementation of BLMS adaptive digital filter (ADF). Compared with the best of the existing DA-based LMS structures, proposed one involves nearly ${L\over 6}$ times adders and $L$ times LUT words, and offers nearly $L$ times throughput of the other. It requires nearly 25% more flip-flops and does not involve variable shifters like those of existing structures. It involves less LUT access per output (LAPO) than the existing structure for block-size higher than 4. For block-size 8 and filter length 64, the proposed structure involves 2.47 times more adders, 15% more flip-flops, 43% less LAPO than the best of existing structures, and offers 5.22 times higher throughput. The number of adders of the proposed structure does not increase proportionately with block size; and the number of flip-flops is independent of block-size. This is a major advantage of the proposed structure for reducing its area delay product (ADP); particularly, when a large order ADF is implemented for higher block-sizes. ASIC synthesis result shows that, the proposed structure for filter length 64, has almost 14% and 30% less ADP and 25% and 37% less EPO than the best of the existing structures for block size 4 and 8, respectively. © 1991-2012 IEEE. Source

Dixit D.,Jaypee University of Engineering & Technology | Dixit D.,The LNM Institute of Information Technology | Sahu P.R.,Indian Institute of Technology Guwahati
IEEE Transactions on Wireless Communications | Year: 2013

Performance of quadrature amplitude modulation (QAM) scheme in two-wave with diffuse power (TWDP) fading environment is analyzed. Closed-form expressions for the exact average symbol error rate (ASER) of general order rectangular QAM (RQAM) and cross QAM (XQAM) schemes are presented using moment generating function of TWDP fading distribution. Obtained ASER expressions are in the form of Appell's (Φ1(·)) and Lauricella's (Φ1 3(·)) hypergeometric functions which can be numerically evaluated using either integral or series representation. Further, closed-form expression for the nth order moment of the received signal-to-noise ratio is derived. Numerical results show excellent agreement with simulation results. © 2002-2012 IEEE. Source

Arya R.K.,Jaypee University of Engineering & Technology
Computers and Chemical Engineering | Year: 2013

Mass transport equations in multicomponent polymeric coatings are nonlinear coupled partial differential equations. These equations were solved using Galerkin's method of finite elements which converts them to ordinary differential equations. Residuals were made orthogonal by using quadratic basis functions. Non-uniform elements were used to capture steep concentration gradient near the top of the coating. Finite element formulation has been solved using ode15s of MATLAB. Results are in very good agreement with the earlier results using different solution techniques. © 2012 Elsevier Ltd. Source

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