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Von Essen C.,French National Center for Scientific Research | Jobstmann B.,French National Center for Scientific Research | Jobstmann B.,Jasper Design Automation | Jobstmann B.,Ecole Polytechnique Federale de Lausanne
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) | Year: 2013

We present a new and flexible approach to repair reactive programs with respect to a specification. The specification is given in linear-temporal logic. Like in previous approaches, we aim for a repaired program that satisfies the specification and is syntactically close to the faulty program. The novelty of our approach is that it produces a program that is also semantically close to the original program by enforcing that a subset of the original traces is preserved. Intuitively, the faulty program is considered to be a part of the specification, which enables us to synthesize meaningful repairs, even for incomplete specifications. Our approach is based on synthesizing a program with a set of behaviors that stay within a lower and an upper bound. We provide an algorithm to decide if a program is repairable with respect to our new notion, and synthesize a repair if one exists. We analyze several ways to choose the set of traces to leave intact and show the boundaries they impose on repairability. We have evaluated the approach on several examples. © 2013 Springer-Verlag.


Jobstmann B.,French National Center for Scientific Research | Staber S.,Jasper Design Automation | Griesmayer A.,Imperial College London | Bloem R.,Graz University of Technology
Journal of Computer and System Sciences | Year: 2012

Knowing that a program has a bug is good, knowing its location is better, but a fix is best. We present a method to automatically locate and correct faults in a finite state system, either at the gate level or at the source level. We assume that the specification is given in Linear Temporal Logic, and state the correction problem as a game, in which the protagonist selects a faulty component and suggests alternative behavior. The basic approach is complete but as complex as synthesis. It also suffers from problems of readability: the correction may add state and logic to the system. We present two heuristics. The first avoids the doubly exponential blowup associated with synthesis by using nondeterministic automata. The second heuristic finds a memoryless strategy, which we show is an NP-complete problem. A memoryless strategy corresponds to a simple, local correction that does not add any state. The drawback of the two heuristics is that they are not complete unless the specification is an invariant. Our approach is general: the user can define what constitutes a component, and the suggested correction can be an arbitrary combinational function of the current state and the inputs. We show experimental results supporting the applicability of our approach. © 2011 Published by Elsevier Inc.


Ali R.,Bournemouth University | Griggio A.,Fondazione Bruno Kessler | Franzen A.,Jasper Design Automation | Dalpiaz F.,University of Trento | Giorgini P.,University of Trento
Lecture Notes in Business Information Processing | Year: 2012

Monitoring the system environment is a key functionality of a self-adaptive system. Monitoring requirements denote the information a self-adaptive system has to capture at runtime to decide upon whether an adaptation action has to be taken. The identification of monitoring requirements is a complex task which can easily lead to redundancy and uselessness in the set of information to monitor and this, consequently, means unjustified instalment of monitoring infrastructure and extra processing time. In this paper, we study the optimization of monitoring requirements. We discuss the case of contextual goal model, which is a requirements model that weaves between variability of goals (functional and non-functional requirements) and variability of context (monitoring requirements) and is meant to be used for modelling mobile and self-adaptive systems requirements. We provide automated analysis -based on a SAT-solver- to process a contextual goal model and find a reduced set of contextual information to monitor guaranteeing that this reduction does not sacrifice the system ability of taking correct adaptation decisions when fulfilling its requirements. © 2012 Springer-Verlag Berlin Heidelberg.


Kranen K.,Jasper Design Automation
IEEE Design and Test | Year: 2014

The EDA industry is up to the technical challenges of delivering the continuous technological breakthroughs needed. Even Wall Street likes EDA, with our public companies outperforming all the major stock indices over the past few years. And some private companies, with very high differentiation, have figured out how to compete against lower-priced, big-EDA solutions and in the process created new business models that are driving sustained growth and profitability. The future of the industry is about enabling design and verification teams understanding their needs and accelerating their innovations. There is also the connectedness across both time and geography that comes from the very products that one creates.


Patent
Jasper Design Automation | Date: 2013-10-02

A first waveform for a circuit design is received. The first waveform includes at least an actual value of a signal of the circuit design at one or more clock cycles. A user input for a cursor is received, and a signal wave overlay is displayed on the first waveform having an appearance corresponding to a location of the cursor. The signal wave overlay indicates a desired value of the signal at one or more clock cycles that is different than the actual value of the signal in the one or more clock cycles. Based on the desired value of the signal indicated by the signal wave overlay, a visualization constraint for the circuit design is generated. The visualization constraint is used to generate a second waveform, where the visualization constraint restricts the second waveform.


Patent
Jasper Design Automation | Date: 2013-10-04

A viewer shows circuit design activities, displaying a signal, its corresponding trace, and the values of the trace over time. A global zoom-in, zoom-out, and zoom-fit are provided over the value display to adjust the time interval covered within the viewer. Non-linear manipulation of the traces within the viewer enables simultaneous zoomed in display of multiple time intervals, and zoomed out display of other time intervals. The non-linear manipulations may be performed within a same display region by designating zoom groups corresponding to the selection of a designated time period of activities of the circuit. Each zoom group may be scaled independently of other timer periods to zoom in or out of activities occurring within the designated time period. A list of behaviors may also be provided. Selection of a behavior generates a separate signal list for signals associated with the behavior and corresponding traces for enhanced debugging.


Patent
Jasper Design Automation | Date: 2013-10-09

A viewer shows circuit design activities, displaying a signal, its corresponding trace, and the values of the trace over time. A global zoom-in, zoom-out, and zoom-fit are provided over the value display to adjust the time interval covered within the viewer. Non-linear manipulation of the traces within the viewer enables simultaneous zoomed in display of multiple time intervals, and zoomed out display of other time intervals. The non-linear manipulations may be performed within a same display region by designating zoom groups corresponding to the selection of a designated time period of activities of the circuit. Each zoom group may be scaled independently of other timer periods to zoom in or out of activities occurring within the designated time period. A list of behaviors may also be provided. Selection of a behavior generates a separate signal list for signals associated with the behavior and corresponding traces for enhanced debugging.


Patent
Jasper Design Automation | Date: 2013-10-31

A method for data propagation analysis. A data propagation diagram for a circuit design is generated. The data propagation diagram includes a plurality of nodes and a plurality of edges connecting the nodes. The nodes represent data locations in the circuit design and the edges represent data propagation paths between the data locations in the circuit design. A signal trace specifying signal values for the circuit design is analyzed to determine whether data at a first data location of the data locations during a first clock cycle is causally related to the data at a second data location of the data locations during a second clock cycle. A visual animation is displayed on the data propagation diagram indicating movement of the data between a first node of the nodes corresponding to the first data location and a second node of the nodes corresponding to the second data location.


News Article | February 12, 2009
Site: www.xconomy.com

Jasper Design Automation, Inc., a privately-held Electronic Design Automation (EDA) company with a mission of making full formal IC verification a competitive advantage for its customers.

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