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Hiroshima Y.,Oi Electrical Co. | Kodama T.,Japan Process Development Co. | Suzuki T.,Shonan Institute of Technology | Watanabe S.,Shonan Institute of Technology
Contemporary Engineering Sciences | Year: 2014

The reduction of pattern area and delay time for logic circuit using newly proposed DTMOS type SGT with the same power consumption compared to that using conventional SGT are described. The reduction of delay time of logic circuit such as inverter and NAND circuit with small channel width using DTMOS type SGT is presented. The delay times of these circuits with DTMOS type SGT can be reduced to 64%-77% compared to that with conventional SGT with supply voltage of 0.5V. Furthermore, using large channel width transistor delay time or channel width with DTMOS type SGT can be reduced to 58%-61% compared to that with conventional SGT using supply voltage of 0.5V. DTMOS type SGT is the promising candidates for realizing high density high speed low power LSI. © 2013 Yu Hiroshima et al. Source


Kodama T.,Japan Process Development Co. | Hiroshima Y.,Oi Electrical Co. | Watanabe S.,Shonan Institute of Technology
Contemporary Engineering Sciences | Year: 2013

The pattern area reduction with SGT and FinFET for LSI, such as inverter, NAND gates, full adder, and row decoder has been newly described. With small channel width of 8F the pattern area of inverter, NAND gates and full adders with SGT can be reduced compared with that with FinFET. This results are useful for designing system LSI for communications. With larger channel width than 8F the pattern area of inverter, NAND gates and full adders with SGT has the tendency to become larger than that with FinFET. This results are useful for designing system LSI for cell library and high end MPU. Furthermore, for designing core circuit, such as row decoder and sense amplifier, smaller pattern area can be realized with SGT compared with that with FinFET. Source


Gu Q.,Hiroshima University | Raut S.,Hiroshima University | Okumura K.-I.,Hiroshima University | Okumura K.-I.,Japan Process Development Co. | And 3 more authors.
Journal of Robotics and Mechatronics | Year: 2015

In this paper, we propose a real-time image mosaicing system that uses a high-frame-rate video sequence. Our proposed system can mosaic 512×512 color images captured at 500 fps as a single synthesized panoramic image in real time by stitching the images based on their estimated frame-to-frame changes in displacement and orientation. In the system, feature point extraction is accelerated by implementing a parallel processing circuit module for Harris corner detection, and hundreds of selected feature points in the current frame can be simultaneously corresponded with those in their neighbor ranges in the previous frame, assuming that frame-to-frame image displacement becomes smaller in high-speed vision. The efficacy of our system for improved feature-based real-time image mosaicing at 500 fps was verified by implementing it on a field-programmable gate array (FPGA)-based high-speed vision platform and conducting several experiments: (1) capturing an indoor scene using a camera mounted on a fast-moving twodegrees- of-freedom active vision, (2) capturing an outdoor scene using a hand-held camera that was rapidly moved in a periodic fashion by hand. © 2015, Fuji Technology Press. All rights reserved. Source


Hiroshima Y.,Oi Electrical Co. | Kodama T.,Japan Process Development Co. | Watanabe S.,Shonan Institute of Technology
IEEJ Transactions on Electronics, Information and Systems | Year: 2012

Stacked type DTMOS which enables to realize both high-speed low-power characteristics of FinFET type DTMOS and small pattern area of stacked transistor has been newly proposed. The delay time of substrate of stacked type DTMOS can be reduced to less than 10% compared with that of conventional FinFET type DTMOS by using the sidewall connection between gate and substrate. By using stacked structure of NMOS with (110) substrate on PMOS with (100) substrate high speed performance with the optimized mobility value can be realized without sacrificing the pattern area. Furthermore, the pattern area of inverter/NAND circuit, LSI for communication and DRAM buffer circuit with stacked type DTMOS has been compared with that of conventional FinFET type DTMOS. Newly proposed stacked type DTMOS is a promising candidate for realizing high performance system LSI such as the microprocessor of GHz operation. © 2012 The Institute of Electrical Engineers of Japan. Source


Kodama T.,Japan Process Development Co. | Hiroshima Y.,Oi Electrical Co. | Watanabe S.,Shonan Institute of Technology
Contemporary Engineering Sciences | Year: 2014

Independent-gate controlled Double Gate SGT (DG SGT) has been newly proposed. Three kinds of DG SGT which use rectangular parallelepiped, U-shaped, and doughnut-shaped silicon pillar have been described. The reduction of pattern area of logic circuit such as inverter and NAND circuit with DG SGT has been estimated. Using DG SGT the pattern area of NAND circuit of small channel width can be reduced to 53-65% compared to that of conventional SGT. Using DG SGT the pattern area of inverter and 4-input NAND with large channel width of 40F can be reduced to 70-75%. Furthermore, the fabrication cost of logic circuit with DG SGT has been described. DG SGT is the promising candidates for realizing small pattern area and low fabrication cost for logic circuit and LSI. © 2013 Takahiro Kodama et al. Source

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