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Golestan S.,Islamic Azad University at Abadan | Ramezani M.,Islamic Azad University at Abadan | Guerrero J.M.,University of Aalborg | Monfared M.,Ferdowsi University of Mashhad
IEEE Transactions on Power Electronics | Year: 2015

To improve the performance of phase-locked loops (PLLs) under adverse grid conditions, incorporating different filtering techniques into their structures have been proposed in the literature. These filtering techniques can be broadly classified into in-loop and preloop filtering techniques depending on their position in the PLL structure. Inspired from the concept of delayed signal cancellation (DSC), the idea of cascaded DSC (CDSC) has recently been introduced as an effective solution to improve the performance of the PLL under adverse grid conditions. However, the focus has been on the application of CDSC operator as the prefiltering stage of PLL, and little work has been conducted on its application as the in-loop filtering stage of PLL. This paper provides a detailed analysis and design of dqCDSC-PLL (PLL with in-loop dq-frame CDSC operator). The study is started with an overview of this PLL. A systematic design method to fine tune its control parameters is then proposed. The performance of the dqCDSC-PLL under different grid scenarios is then evaluated in detail. It is then shown that how using the proportional-integral-derivative controller as the loop filter can improve the response time of dqCDSC-PLL. A detailed comparison between the dqCDSC-PLL and moving average filter (MAF) based PLL (MAF-PLL) is then carried out. Through a detailed mathematical analysis, it is also shown that these PLLs are equivalent under certain conditions. The suggested guidelines in this paper make designing the dqCDSC-PLL a simple and straightforward procedure. Besides, the analysis performed in this paper provides a useful insight for designers about the advantages/disadvantages of dqCDSC-PLL for their specific applications. © 2012 IEEE.


Monfared M.,Ferdowsi University of Mashhad | Golestan S.,Islamic Azad University at Abadan | Guerrero J.M.,University of Aalborg
IEEE Transactions on Industrial Electronics | Year: 2014

Control of three-phase power converters in the synchronous reference frame (SRF) is now a mature and well-developed research topic. However, for single-phase converters, it is not as well established as three-phase applications. This paper deals with the design of an SRF multiloop control strategy for single-phase inverter-based islanded distributed generation systems. The proposed controller uses an SRF proportional-integral controller to regulate the instantaneous output voltage, a capacitor current shaping loop in the stationary reference frame to provide active damping and improve both transient and steady-state performances, a voltage decoupling feedforward to improve the system robustness, and a multiresonant harmonic compensator to prevent low-order load current harmonics to distort the inverter output voltage. Since the voltage loop works in the SRF, it is not straightforward to fine tune the control parameters and evaluate the stability of the whole closed-loop system. To overcome this problem, the stationary reference frame equivalent of the voltage loop is derived. Then, a step-by-step systematic design procedure based on a frequency response approach is presented. Finally, the theoretical achievements are supported by experimental results. © 1982-2012 IEEE.


Golestan S.,Islamic Azad University at Abadan | Monfared M.,Ferdowsi University of Mashhad | Freijedo F.D.,University of Vigo | Guerrero J.M.,University of Aalborg
IEEE Transactions on Industrial Electronics | Year: 2013

Recently, several advanced phase-locked loop (PLL) techniques have been proposed for single-phase applications. Among these, the Park-PLL and the second-order-generalized-integrator-based PLL are very attractive, owing to their simple digital implementation, low computational burden, and desired performance under frequency-varying and harmonically distorted grid conditions. Despite the wide acceptance and use of these two advanced PLLs, no comprehensive design guidelines to fine-tune their parameters have been reported yet. Through a detailed mathematical analysis, it is shown that these two PLL structures are equivalent to each other, from the control point of view. Then, a linearized model is developed which is valid for both PLLs. The derived model significantly simplifies the stability analysis and the parameter design. To fine-tune the PLL parameters, a systematic design approach is suggested afterward, which guarantees a fast dynamic response, a high disturbance rejection ability, and a robust performance. Finally, the simulation and experimental results are presented to support the theoretical analysis. © 2012 IEEE.


Golestan S.,Islamic Azad University at Abadan | Monfared M.,Ferdowsi University of Mashhad | Freijedo F.D.,University of Vigo | Guerrero J.M.,University of Aalborg
IEEE Transactions on Power Electronics | Year: 2012

One of the most important aspects for the proper operation of the single-phase grid-tied power-conditioning systems is the synchronization with the utility grid. Among various synchronization techniques, phase locked loop (PLL)-based algorithms have found a lot of interest for the advantages they present. Typically, the single-phase PLLs use a sinusoidal multiplier as the phase detector (PD). These PLLs are generally referred to as the power-based PLL (pPLL). In this paper, the drawbacks associated with the pPLL technique (i.e., the sensitivity to the grid voltage variations, and the double-frequency oscillations that appear in the estimated phase/frequency) are discussed in detail, and some of the previously reported solutions are examined. Then, to overcome these drawbacks, a simple and effective technique, called the double-frequency and amplitude compensation (DFAC) method is proposed. The effectiveness of the proposed method is evaluated through a detailed mathematical analysis. A systematic design method to fine-tune the PLL parameters is then suggested, which guarantees a fast transient response, a high disturbance rejection capability, and a robust performance. Finally, the simulation and experimental results are presented, which highlight the effectiveness of the proposed PLL. © 2012 IEEE.


Golestan S.,Islamic Azad University at Abadan | Monfared M.,Ferdowsi University of Mashhad | Freijedo F.D.,Gamesa | Guerrero J.M.,University of Aalborg
IEEE Transactions on Power Electronics | Year: 2013

A phase-locked loop (PLL) is a closed-loop feedback control system, which synchronizes its output signal in frequency as well as in phase with an input signal. The phase detector, the loop filter, and the voltage controlled oscillator are the key parts of almost all PLLs. Within the areas of power electronics and power systems, which are focused on in this paper, the PLLs typically employ a proportional-integral controller as the loop filter, resulting in a type-2 control system (a control system of type-N has N poles at the origin in its open-loop transfer function). Recently, some attempts have been made to design type-3 PLLs, either by employing a specific second-order controller as the loop filter, or by implementing two parallel tracking paths for the PLL. For this type of PLLs, however, the advantages and limitations are not clear at all, as the results reported in different literature are contradictory, and there is no detailed knowledge about their stability and dynamic characteristics. In this paper, different approaches to realize a type-3 PLL are examined first. Then, a detailed study of dynamics and analysis of stability, followed by comprehensive parameters design guidelines for a typical type-3 PLL are presented. Finally, to get insight into the advantages/ limitations of this type of PLLs, the performance of a well-tuned type-3 PLL is compared with a conventional synchronous reference frame PLL (which is a type-2 PLL) through extensive experimental results and some theoretical discussions. © 1986-2012 IEEE.


Golestan S.,Islamic Azad University at Abadan | Ramezani M.,Islamic Azad University at Abadan | Guerrero J.M.,University of Aalborg | Freijedo F.D.,Gamesa | Monfared M.,Ferdowsi University of Mashhad
IEEE Transactions on Power Electronics | Year: 2014

The phase-locked loops (PLLs) are probably the most widely used synchronization technique in grid-connected applications. The main challenge that is associated with the PLLs is how to precisely and fast estimate the phase and frequency, when the grid voltage is unbalanced and/or distorted. To overcome this challenge, incorporating moving average filter(s) (MAF) into the PLL structure has been proposed in some recent literature. An MAF is a linear-phase finite-impulse-response filter, which can act as an ideal low-pass filter, if certain conditions hold. The main aim of this paper is to present the control design guidelines for a typical MAF-based PLL. The paper starts with the general description of MAFs. The main challenge associated with using the MAFs is then explained, and its possible solutions are discussed. The paper then proceeds with a brief overview of the different MAF-based PLLs. In each case, the PLL block diagram description is shown, the advantages and limitations are briefly discussed, and the tuning approach (if available) is evaluated. The paper then presents two systematic methods to design the control parameters of a typical MAF-based PLL: one for the case of using a proportional-integral (PI) type loop filter (LF) in the PLL, and the other for the case of using a proportional-integral-derivative (PID) type LF. Finally, the paper compares the performance of a well-tuned MAF-based PLL when using the PI-type LF with the results of using the PID-type LF, which provides useful insights into their capabilities and limitations. © 2013 IEEE.


Golestan S.,Islamic Azad University at Abadan | Monfared M.,Ferdowsi University of Mashhad | Freijedo F.D.,Gamesa | Guerrero J.M.,University of Aalborg | Guerrero J.M.,University of Barcelona
IEEE Transactions on Industrial Electronics | Year: 2014

Control Parameters design of a three-phase synchronous reference frame phase locked loop (SRF-PLL) with a prefiltering stage (acting as the sequence separator) is not a trivial task. The conventional way to deal with this problem is to neglect the interaction between the SRF-PLL and prefiltering stage, and treat them as two separate systems. This approach, although very simple, is not optimum as the prefiltering stage and the SRF-PLL may have comparable dynamics. The aim of this paper is to develop a systematic and efficient approach to design the control parameters of the SRF-PLL with prefiltering stage. To this end, the paper first optimizes the performance of the prefiltering stage in detection of the sequence components. The paper then proceeds to reduce the interaction between the prefiltering stage and SRF-PLL, which is achieved by employing a derivative-filtered proportional-integral-derivative controller as the loop filter (instead of the commonly adopted proportional-integral controller) and arranging a pole-zero cancellation. The suggested method is simple and efficient, and is applicable to the joint operation of different sequence separation techniques and the SRF-PLL. The effectiveness of the suggested design approach is confirmed through extensive experimental results. © 1982-2012 IEEE.


Golestan S.,Islamic Azad University at Abadan | Monfared M.,Ferdowsi University of Mashhad | Freijedo F.D.,Gamesa
IEEE Transactions on Power Electronics | Year: 2013

In grid-connected applications, the synchronous reference frame phase-locked loop (SRF-PLL) is a commonly used synchronization technique due to the advantages it offers such as ease of implementation and robust performance. Under ideal grid conditions, the SRF-PLL enables a fast and accurate phase/frequency detection; however, unbalanced and distorted grid conditions highly degrade its performance. To overcome this drawback, several advanced PLLs have been proposed, such as the multiple reference frame-based PLL, the dual second-order generalized integrator-based PLL, and the multiple complex coefficient filter-based PLL. In this paper, a comprehensive design-oriented study of these advanced PLLs is presented. The starting point of this study is to derive the small-signal model of the aforementioned PLLs, which simplifies the parameter design and the stability analysis. Then, a systematic design procedure to fine tune the PLLs parameters is presented. The stability margin, the transient response, and the disturbance rejection capability are the key factors that are considered in the design procedure. Finally, the experimental results are presented to support the theoretical analysis. © 1986-2012 IEEE.


Bakhtiari S.,Islamic Azad University at Abadan
Advances in Information Sciences and Service Sciences | Year: 2011

Currently, with the emergence of mobile payment systems and service-oriented architecture, the focus has shifted to utilizing modern service industry in mobile commerce. One of the important uses of mobile applications is transforming the mobile phone into a mobile wallet with digital cash that supports both anonymity (as real cash) and security [3]. Hence, in this article we propose applying service-oriented architecture in a mobile payment system called Mobi Cash [17] to provide fully anonymity for mobile users.


Monfared M.,Ferdowsi University of Mashhad | Golestan S.,Islamic Azad University at Abadan
Renewable and Sustainable Energy Reviews | Year: 2012

Small-scale renewable energy sources, such as small hydro turbines, roof-mounted photovoltaic and wind generation systems, and commercially available fuel cells are usually connected to the single-phase distribution grid through a voltage source converter. To regulate the power exchange with the single-phase grid, and at the same time, reduce the harmonic distortions in the ac current, different current control structures have already been proposed, among which the current hysteresis control, the voltage oriented control, and the proportional-resonant based control have found more attentions. This paper provides an overview of the main characteristics of these control strategies. Also, some implementation aspects such as the fictitious signal generation and the single-phase grid synchronization techniques are discussed. Finally, through extensive simulations a comparative study of the presented control strategies is presented. The simulations are supported by experiments. © 2012 Elsevier Ltd. All rights reserved.

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