IRoC Technologies

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Glorieux M.,IROC Technologies | Evans A.,IROC Technologies | Ferlet-Cavrois V.,European Space Agency | Boatella-Polo C.,European Space Agency | And 4 more authors.
IEEE Transactions on Nuclear Science | Year: 2017

Single Event Transients (SETs) are a major concern for space applications, particularly when hardened flip flops are used to reduce the sensitivity of sequential logic. Characterizing SETs is complex as both the cross section and the pulse width must be measured. In the 65 nm test chip presented in this paper, three different SET measurement circuits, implemented on the same die, are characterized and compared. Using these SET detectors, heavy-ion test results are presented. The detectors are compared and a detailed study of the SET sensitivity of multiple gates operating at different logical, load and voltage conditions is presented. © 2016 IEEE.


Ebrahimi M.,Karlsruhe Institute of Technology | Evans A.,IROC Technologies | Tahoori M.B.,Karlsruhe Institute of Technology | Costenaro E.,IROC Technologies | And 3 more authors.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | Year: 2015

Radiation-induced soft errors have become a key challenge in advanced commercial electronic components and systems. We present the results of a soft error rate (SER) analysis of an embedded processor. Our SER analysis platform accurately models generation, propagation, and masking effects starting from a technology response model derived using TCAD simulations at the device level all the way to application masking. The platform employs a combination of accurate models at the device level, analytical error propagation at gate level, and fault emulation at the architecture/application level to provide the detailed contribution of each component (flip-flops, combinational gates, and SRAMs) to the overall SER. At each stage in the modeling hierarchy, an appropriate level of abstraction is used to propagate the effect of errors to the next higher level. Unlike previous studies which are based on very simple test chips, analyzing the entire processor gives more insight into the relative contributions of combinational and sequential SER. The results of this analysis can assist circuit designers to adopt effective hardening techniques to reduce the overall SER while meeting the required power and performance constraints. © 1982-2012 IEEE.


Evans A.,IRoC Technologies | Alexandrescu D.,IRoC Technologies | Costenaro E.,IRoC Technologies | Chen L.,Karlsruhe Institute of Technology
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium, IOLTS 2013 | Year: 2013

With increased device integration and a gradual trend toward higher operating frequencies, the effect of radiation induced transients in combinatorial logic (SETs) can no longer be ignored. Electrical, logical and temporal masking prevent the majority of SETs from becoming functional failures. Current work on SET analysis starts from a gate-level circuit representation, however, in an industrial design cycle, by the time a gate-level netlist is available, it is too late to make design changes. We propose a hierarchical SET analysis methodology that can be applied at the RTL level. The SET sensitivity of the cell library and the masking characteristics of standard combinatorial design blocks are pre-characterized and stored in compact models. The SET sensitivity of a complex circuit is then calculated by decomposing it into blocks and combining the compact SET models. Experimental results are presented for an ALU implemented in the NanGate library. © 2013 IEEE.


Costenaro E.,IRoC Technologies | Alexandrescu D.,IRoC Technologies | Belhaddad K.,IRoC Technologies | Nicolaidis M.,TIMA Laboratory
Journal of Electronic Testing: Theory and Applications (JETTA) | Year: 2013

Single Event Transients are considerably more difficult to model, simulate and analyze than the closely-related Single Event Upsets. The work environment may cause a myriad of distinctive transient pulses in various cell types that are used in widely different configurations. We present practical methods to help characterizing the standard cell library using dedicated tools and results from radiation testing. Furthermore, we analyze the SET propagation in logic networks using a standard (reference) serial fault simulation approach and an accelerated fault simulation technique, taking in account both logic and temporal considerations. The accelerated method provides similar results as the reference approach while offering a considerable increase in the simulation speed. However, the simulation approach may not be feasible for large (multi-million cells) designs that could benefit from static analysis methods. We benchmark the results of a static, probabilistic approach against the reference and accelerated methods. Finally, we discuss the integration of the SET analysis in a complete Soft Error Rate analysis flow. © 2013 Springer Science+Business Media New York.


Evans A.,IROC Technologies | Nicolaidis M.,Ecole Polytechnique - Palaiseau | Wen S.-J.,Cisco Systems | Asis T.,Vanderbilt University
Proceedings - International Symposium on Quality Electronic Design, ISQED | Year: 2013

In large SoCs, managing the effects of soft-errors in flip-flops is essential, however, selective mitigation is necessary to minimize the area and power costs. The identification of the optimal set of flip-flops to protect typically requires compute-intensive fault-injection campaigns. We present new techniques which group similar flip-flops into clusters to significantly reduce the number of fault injections. The number of required fault injections can be significantly lower than the total number of flip-flops and in one industrial design with over 100,000 flip-flops, by simulating only 2,100 fault injections, the technique identified a set of 4.1% of the flip-flops, which when protected, reduced the critical failure rate by a factor of 7x. © 2013 IEEE.


Alexandrescu D.,IRoC Technologies
Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011 | Year: 2011

Memory blocks are important features of any design, in terms of functionality, silicon area and reliability. Embedded SRAM instances are critical contributors to the overall Soft Error Rate of the system, requiring a careful consideration of the reliability aspects and adequate sizing of the error mitigation capabilities. While error detecting and correcting codes are widely available and particularly effective against most types of Single Event Effects, Multiple Bit Upsets and progressive errors accumulation may defeat the error correction capabilities of standard SECDED codes. Accordingly, the paper presents an overall approach to the structural and functional SER analysis of the memory instances in addition to error mitigation efficiency estimation. Moreover, intrinsic, nominal, SER figures are not a realistic indicator of the memory behavior for a given application. We propose instead, an opportunity window metric, associated to the notion of data lifetime in the memory, as extracted from functional simulations. Lastly, based on the opportunity window figures, targeted and efficient fault simulation campaigns can be prepared to estimate high-level functional failures induced by Single Events. The overall memory SER evaluation aims at assisting the designers to improve the performances of the design and to document the reliability figures of the system. © 2011 IEEE.


Alexandrescu D.,IRoC Technologies | Costenaro E.,IRoC Technologies
Proceedings of the 2012 IEEE 18th International On-Line Testing Symposium, IOLTS 2012 | Year: 2012

Single Event Effects strongly impact the reliability of electronic circuits and systems, requiring careful SER characterization and adequately sized mitigation strategy. The SER study aims at providing relevant information about the circuit behavior in the specified working environment, in terms of Functional Failures rates, criticality and so on. Ultimately, the error mitigation efforts are directed at improving the function of the circuit in the presence of SEE by either reducing the failure occurrence rate or the failure impact. However, when dealing with SEEs affecting highly sophisticated electronic designs, functional issues are one of the most complex aspects to reliably characterize. This paper aims at proposing and evaluating several fault characterization techniques, meant to approximate the functional failures induced by Single Event Upsets in complex circuits, very early in the design flow. The two main contributions of our efforts consist in a differential fault simulation approach based on standard simulation tools and a novel parallel, SEE-optimized, stand-alone simulation tool. Both methods accurately evaluate the immediate propagation of SEE-induced faults and predict the long-term behavior of the faulty circuit running a specified application. The works described in this paper also benefit from various optimization techniques targeting lower simulation costs (in terms of CPU and man-power) while preserving the accuracy of the results. Ultimately, the results of each method compare positively with reference data obtained from an exhaustive fault simulation campaign. This encouraging outcome suggests that we can reliably obtain highly informative functional error information while spending reasonable resources (CPU, man-power, time). © 2012 IEEE.


Alexandrescu D.,iRoC Technologies
2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010 | Year: 2010

Single Event Effects (SEEs) may cause system downtime, data corruption and maintenance incidents. Thus, the SEE are a threat to the overall system reliability, causing designers to be increasingly concerned about the analysis and the mitigation of radiation-induced failures, even for commercial systems performing in a natural working environment. Experts and reliability engineers are called in to support chip designers in the management of Single Event Effects. To this goal, we present a design-flow-oriented Soft Error Rate analysis methodology geared to allow practical and concrete decisions concerning implementation, design and functional choices in order to minimize SEEs impact on circuit and system behavior.


Pontarelli S.,University of Rome Tor Vergata | Ottavi M.,University of Rome Tor Vergata | Evans A.,IRoC Technologies | Wen S.-J.,Cisco Systems
Proceedings -Design, Automation and Test in Europe, DATE | Year: 2013

This paper presents an innovative approach to detect soft errors in Ternary Content Addressable Memories (TCAMs) based on the use of Bloom Filters. The proposed approach is described in detail and its performance results are presented. The advantages of the proposed method are that no modifications to the TCAM device are required, the checking is done on-line and the approach has low power and area overheads. © 2013 EDAA.


A circuit comprises a combinatory logic circuit having one input and one output (A). First and second sampling elements (92, 93) are connected to the output (A) and sample this output respectively at the activation of a first and second latching events determined by an event of first and second clock signals (CK). The event of second clock signal (CK) is delayed with respect to the event of a first clock by a delay which is shorter than the clock period. An analysis circuit (95) analyzes the outputs of the first and the second sampling elements and provides an error detection signal. The analysis circuit (95) sets the error detection signal (E) at the pre-determined value if the outputs of the first and second sampling elements (92, 93) are different. The circuit is used in a first operating mode in which the event of a second clock (CK) determining the second latching event is delayed with respect to the event of first clock (CK) determining the first latching event by a delay which is larger than a largest delay of the circuit.

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