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Alexandrescu D.,IRoC Technologies
Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011 | Year: 2011

Memory blocks are important features of any design, in terms of functionality, silicon area and reliability. Embedded SRAM instances are critical contributors to the overall Soft Error Rate of the system, requiring a careful consideration of the reliability aspects and adequate sizing of the error mitigation capabilities. While error detecting and correcting codes are widely available and particularly effective against most types of Single Event Effects, Multiple Bit Upsets and progressive errors accumulation may defeat the error correction capabilities of standard SECDED codes. Accordingly, the paper presents an overall approach to the structural and functional SER analysis of the memory instances in addition to error mitigation efficiency estimation. Moreover, intrinsic, nominal, SER figures are not a realistic indicator of the memory behavior for a given application. We propose instead, an opportunity window metric, associated to the notion of data lifetime in the memory, as extracted from functional simulations. Lastly, based on the opportunity window figures, targeted and efficient fault simulation campaigns can be prepared to estimate high-level functional failures induced by Single Events. The overall memory SER evaluation aims at assisting the designers to improve the performances of the design and to document the reliability figures of the system. © 2011 IEEE.

Reviriego P.,Antonio de Nebrija University | Demirci M.,Aselsan | Evans A.,IRoC Technologies | Maestro J.A.,Antonio de Nebrija University
IEEE Transactions on Circuits and Systems II: Express Briefs | Year: 2016

Single error correction (SEC) codes are widely used to protect data stored in memories and registers. In some applications, such as networking, a few control bits are added to the data to facilitate their processing. For example, flags to mark the start or the end of a packet are widely used. Therefore, it is important to have SEC codes that protect both the data and the associated control bits. It is attractive for these codes to provide fast decoding of the control bits, as these are used to determine the processing of the data and are commonly on the critical timing path. In this brief, a method to extend SEC codes to support a few additional control bits is presented. The derived codes support fast decoding of the additional control bits and are therefore suitable for networking applications. © 2004-2012 IEEE.

Alexandrescu D.,IRoC Technologies
2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010 | Year: 2010

Single Event Effects (SEEs) may cause system downtime, data corruption and maintenance incidents. Thus, the SEE are a threat to the overall system reliability, causing designers to be increasingly concerned about the analysis and the mitigation of radiation-induced failures, even for commercial systems performing in a natural working environment. Experts and reliability engineers are called in to support chip designers in the management of Single Event Effects. To this goal, we present a design-flow-oriented Soft Error Rate analysis methodology geared to allow practical and concrete decisions concerning implementation, design and functional choices in order to minimize SEEs impact on circuit and system behavior.

Evans A.,IRoC Technologies | Nicolaidis M.,Ecole Polytechnique - Palaiseau | Wen S.-J.,Cisco Systems | Asis T.,Vanderbilt University
Proceedings - International Symposium on Quality Electronic Design, ISQED | Year: 2013

In large SoCs, managing the effects of soft-errors in flip-flops is essential, however, selective mitigation is necessary to minimize the area and power costs. The identification of the optimal set of flip-flops to protect typically requires compute-intensive fault-injection campaigns. We present new techniques which group similar flip-flops into clusters to significantly reduce the number of fault injections. The number of required fault injections can be significantly lower than the total number of flip-flops and in one industrial design with over 100,000 flip-flops, by simulating only 2,100 fault injections, the technique identified a set of 4.1% of the flip-flops, which when protected, reduced the critical failure rate by a factor of 7x. © 2013 IEEE.

Pontarelli S.,University of Rome Tor Vergata | Ottavi M.,University of Rome Tor Vergata | Evans A.,IRoC Technologies | Wen S.-J.,Cisco Systems
Proceedings -Design, Automation and Test in Europe, DATE | Year: 2013

This paper presents an innovative approach to detect soft errors in Ternary Content Addressable Memories (TCAMs) based on the use of Bloom Filters. The proposed approach is described in detail and its performance results are presented. The advantages of the proposed method are that no modifications to the TCAM device are required, the checking is done on-line and the approach has low power and area overheads. © 2013 EDAA.

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