Sainte-Foy-lès-Lyon, France
Sainte-Foy-lès-Lyon, France

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Patent
IPDIA Inc | Date: 2015-03-25

The invention relates to a capacitor structure (2) comprising a silicon substrate (4) with first and second sides (6, 8), a double double Metal Insulator Metal trench capacitor (10) including a basis electrode (12), an insulator layer (16, 20), a second and a third conductive layers (18, 22); and comprising a second pad (26) and a fourth pad (30) coupled to the basis electrode (12), a first pad (24) and a third pad (28) coupled together, the first pad (24) being located on the same substrate side than the second pad (26), the third pad (28) being located on the same substrate side than the fourth pad (30), the third pad (28) being coupled to the second conductive layer (18), said second conductive layer (18) being flush with or protruding from the opposite second side (8).


Patent
IPDIA Inc | Date: 2016-07-13

A capacitor 3D-cell formed on a silicon substrate is designed for producing low equivalent serial resistance and high capacitor surface-density. It combines a trench capacitor structure, multiple contact pads to at least one of the electrodes and a track which connects the electrode through the multiple contact pads so as to bypass said electrode between trench portions which are located apart from each other.


Patent
IPDIA Inc | Date: 2017-02-01

The invention relates to a capacitor structure (2) comprising a silicon substrate (4) with first and second sides (6, 8), a double double Metal Insulator Metal trench capacitor (10) including a basis electrode (12), an insulator layer (16, 20), a second and a third conductive layers (18, 22); and comprising a second pad (26) and a fourth pad (30) coupled to the basis electrode (12), a first pad (24) and a third pad (28) coupled together, the first pad (24) being located on the same substrate side than the second pad (26), the third pad (28) being located on the same substrate side than the fourth pad (30), the third pad (28) being coupled to the second conductive layer (18), said second conductive layer (18) being flush with or protruding from the opposite second side (8).


A semiconductor device comprising at least two holes (18, 20) realised in a substrate (6), having each a width and a depth, and forming a diode (4), wherein the substrate (6) has a determined type of doping, wherein the inner wall of each hole (18, 20) is doped so that its doping is of the other type than the doping of the substrate (6), and wherein the width and/or the depth of a hole (18, 20) is different from the width and/or the depth of a neighboring hole.


Patent
IPDIA Inc and French Atomic Energy Commission | Date: 2014-10-29

A Metal-Insulator-Metal type capacitor structure (1) comprising a substrate (2), a first electrically insulating layer (14) placed on the substrate (2), a lower electrode (6) placed on the first insulating layer (14), a layer of structured metal (12) comprising a plurality of pores disposed on the lower electrode (6), a MIM capacitor (4) comprising a first conductive layer (18) placed on the structured metal layer (12) in contact with the lower electrode (6) and inside the pores, a dielectric layer (20) covering the first conductive layer (18), a second conductive layer (24) covering the dielectric layer (20) in contact with an upper electrode (8) placed on the MIM capacitor (4) and a second electrically insulating layer (16) placed on the upper electrode (8).


Patent
IPDIA Inc | Date: 2013-06-12

The invention relates to an interposer device comprising a doped silicon substrate (1) having an epitaxial layer (24) on a first side and two through vias (11, 12) extending from the first side to a second side opposite to the first side of the doped silicon substrate. Each through via comprises a volume of doped silicon substrate delimited by a surrounding trench (7) extending from the first to the second side of the doped silicon substrate such that said surrounding trench is arranged so as to electrically isolate the doped silicon substrate surrounded by said trench. First and second conductive layers (121, 122) are laid respectively on first and second sides of the first through via so as to be electrically connected together and third and fourth conductive layers (112, 111) are laid respectively on surfaces of the second through via so as to be electrically connected together. The first (122) and third (112) conductive layers are connected together by means of a back-to-back diode (35) wherein the diodes are isolated by a diode trench (6) having a depth at least equal to that of the epitaxial layer (24). A method of forming the interposer device is also provided.


A semiconductor die according to this invention comprises a via realised in a bulk material (2). The via has an inner metallic conductor (28) isolated by a dielectric layer (17, 20) from a surrounding conductive area (16). The bulk material (2) is chosen in a set of doped semiconductor materials containing n-type and p-type materials. The surrounding conductive area (16) is in contact with the bulk material (2) and the surrounding conductive area (16) is made from a material chosen in a set of doped semiconductor materials containing n-type and p-type materials, the surrounding conductive area material being from one type among the n-type and the p-type, and the bulk material being from the other type among said n-type and said p-type.


A semiconductor device comprising at least two holes (18, 20) realised in a substrate (6), having each a width and a depth, and forming a diode (4), wherein the substrate (6) has a determined type of doping, wherein the inner wall of each hole (18, 20) is doped so that its doping is from the other type than the doping of the substrate (6), and wherein the width and/or the depth of a hole (18, 20) is different from the width and/or the depth of a neighboring hole.


Patent
IPDIA Inc | Date: 2015-09-30

The invention relates to a capacitor structure (2) comprising a silicon substrate (4) with first and second sides (6, 8), a trench capacitor (10) including a basis electrode (12), a multilayer stack comprising at least one of an even elementary sequence of layers and/or one of an odd elementary sequence of layers, wherein an even/odd elementary sequence of layers comprises an insulator layer (16, 20), an even/odd conductive layer (18, 22); and comprising a second pad (26) and a fourth pad (30) coupled to the basis electrode (12), a first pad (24) and a third pad (28) coupled together, the first pad (24) being located on the same substrate side than the second pad (26), the third pad (28) being located on the same substrate side than the fourth pad (30), the third pad (28) being coupled to an even conductive layer (18), said even conductive layer (18) being flush with or protruding from the opposite second side (8).


An integration substrate for a system in package comprises a through-substrate via and a trench capacitor wherein with a trench filling that includes at least four electrically conductive capacitor-electrode layers in an alternating arrangement with dielectric layers. - The capacitor-electrode layers are alternatingly connected to a respective one of two capacitor terminals provided on the first or second substrate side. The trench capacitor and the through-substrate via are formed in respective trench openings and via openings in the semiconductor substrate , which have an equal lateral extension exceeding 10 micrometer. This structure allows, among other advantages, a particularly cost-effective fabrication of the integration substrate because the via openings and the trench openings in the substrate can be fabricated simultaneously.

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