Milpitas, CA, United States
Milpitas, CA, United States

Intersil Corporation is an American global company formed in August 1999 through the acquisition of the semiconductor business of Harris Corporation. Intersil is a power management IC company, specializing in the development of highly efficient power management and precision analog technology for applications in industrial, infrastructure, mobile, automotive and aerospace. Wikipedia.

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Patent
Intersil | Date: 2016-04-20

On embodiment pertains to an apparatus including a current share control circuit configured to receive a first sample inductor current sense signal representative of a current in a first power stage, configured to receive from a data bus a second sample inductor current sense signal from a fixed reference phase, and which generates a trim signal. A first control loop having an output configured to be coupled to an input of the first power stage, and configured to receive a signal representative of an output voltage and the trim signal.


A voltage regulator including a converter and a modulator. The converter includes a switching circuit coupled to an inductor for converting an input voltage to an output voltage. The modulator controls the switching circuit in a buck mode of operation, a boost mode of operation, and an intermediate buck-boost mode of operation. During the buck-boost mode of operation, the modulator controls the switching circuit during each switching cycle to sequentially switch between three different switching states, including a first switching state that applies the input voltage across the inductor, a second switching state that applies a difference between the input and output voltages across the inductor, and a third switching state that applies the output voltage across the inductor. The modulator is controlled based on voltage applied across or current flowing through the inductor to regulate the output voltage to a target level.


Patent
Intersil | Date: 2017-03-30

A hysteretic current mode buck-boost voltage regulator including a buck-boost voltage converter, a switching controller, a window circuit, a ramp circuit, and a timing circuit. The timing circuit may be additional ramp circuits. The voltage converter is toggled between first and second switching states during a boost mode, is toggled between third and fourth switching states during a buck mode, and is sequentially cycled through each switching state during a buck-boost mode. The ramp circuit develops a ramp voltage that simulates current through the voltage converter, and switching is determined using the ramp voltage compared with window voltages provided by the window circuit. The window voltages establish frequency, and may be adjusted based on the input and output voltages. The timing circuit provides timing indications during the buck-boost mode to ensure that the second and fourth switching states have approximately the same duration to provide symmetry of the ramp signal.


A system, DC-DC converter, and compensation method and circuit for a DC-DC converter are disclosed. For example, a compensation circuit for a DC-DC converter is disclosed. The compensation circuit includes an integrator circuit configured to receive and integrate a first voltage signal, a differential difference amplifier circuit coupled to the integrator circuit and configured to generate a first filter transfer function associated with the integrated first voltage signal, and a switched capacitor filter circuit coupled to the differential difference amplifier circuit and configured to generate a second filter transfer function, wherein the differential difference amplifier is further configured to output a second voltage signal responsive to the first filter transfer function and the second filter transfer function. In one implementation, the compensation circuit is a type-III switched capacitor filter (SCF) compensation circuit.


Patent
Intersil | Date: 2016-11-07

Embodiments disclosed herein provide for a circuit including first die having an active side and a backside, wherein the first die is flip-chip mounted to a carrier. The circuit also includes a second die stacked on the backside of the first die, wherein the second die is stacked on the first die such that a backside of the second die is facing the backside of the first die and an active side of the second die faces away from the first die.


Patent
Intersil | Date: 2016-11-16

Body contact layouts for semiconductor structures are disclosed. In at least one exemplary embodiment, a semiconductor structure comprises: a plurality of gates disposed on a semiconductor layer, each gate extending parallel to a y-axis in a coordinate space; a source region disposed between two of the plurality of gates; a plurality of body contacts disposed in each source region; and wherein a portion of each source region, adjacent to the gate, has a width extending parallel to the y-axis that is greater than the width of the source region parallel to the y-axis at a distance on an x-axis from the gate.


One embodiment pertains to a method including determining the duty cycle of a PWM signal, operating in valley current control mode when the duty cycle is greater than fifty percent, operating in peak current control mode when the duty cycle is less than fifty percent, and including, commencing a PWM pulse upon the occurrence of a pulse of a first clock signal pulse, and terminating the PWM pulse upon a level of a signal exceeding a positive window threshold.


A controller for controlling operation of a switching regulator including a modulator, a discontinuous conduction mode (DCM) controller, an audible DCM (ADCM) controller, and a sub-sonic discontinuous conduction mode (SBDCM) controller. The modulator generally operates in a continuous conduction mode. The DCM controller modifies operation to DCM during low loads. The ADCM controller detects when the switching frequency is less than a super-sonic frequency threshold and modifies operation to maintain the switching frequency at a super-sonic frequency level. The SBDCM controller detects a sub-sonic operating condition during ADCM operation and responsively inhibits operation of the ADCM mode controller to allow a SBDCM mode within a sub-sonic switching frequency range. The SBDCM operating mode allows for efficient connected standby operation. The SBDCM controller allows operation to return to other modes when the switching frequency increases above the subsonic level.


Embodiments of the subject application provide for a circuit comprising: a lead frame having a first plurality of exposed terminals, the lead frame defining a plane; a laminate substrate in the plane defined by the lead frame, adjacent to the lead frame, and electrically coupled to the lead frame, the laminate substrate having a first surface including a second plurality of exposed terminals and a second surface opposite the first surface; a first one or more dies mounted on the lead frame and electrically coupled to the lead frame; and a second one or more dies mounted on the second surface of the laminate substrate and electrically coupled to the laminate substrate.


An embodiment of a circuit includes a circuit module and an inductor disposed over and electrically coupled to the module. Disposing the inductor over the module may reduce the area occupied by the circuit as compared to a circuit where the inductor is disposed adjacent to the module, or to a circuit where the inductor is disposed in the module adjacent to other components of the module. Furthermore, disposing the inductor outside of the module may allow one to install or replace the inductor.

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