Santa Clara, CA, United States

Intel Corporation

www.intel.com
Santa Clara, CA, United States

Intel Corporation is an American multinational corporation headquartered in Santa Clara, California. Intel is one of the world's largest and highest valued semiconductor chip makers, based on revenue. It is the inventor of the x86 series of microprocessors, the processors found in most personal computers.Intel Corporation, founded on July 18, 1968, is a portmanteau of Integrated Electronics . Intel also makes motherboard chipsets, network interface controllers and integrated circuits, flash memory, graphic chips, embedded processors and other devices related to communications and computing. Founded by semiconductor pioneers Robert Noyce and Gordon Moore and widely associated with the executive leadership and vision of Andrew Grove, Intel combines advanced chip design capability with a leading-edge manufacturing capability. Though Intel was originally known primarily to engineers and technologists, its "Intel Inside" advertising campaign of the 1990s made it a household name, along with its Pentium processors.Intel was an early developer of SRAM and DRAM memory chips, and this represented the majority of its business until 1981. Although Intel created the world's first commercial microprocessor chip in 1971, it was not until the success of the personal computer that this became its primary business. During the 1990s, Intel invested heavily in new microprocessor designs fostering the rapid growth of the computer industry. During this period Intel became the dominant supplier of microprocessors for PCs, and was known for aggressive and sometimes illegal tactics in defense of its market position, particularly against Advanced Micro Devices , as well as a struggle with Microsoft for control over the direction of the PC industry.The 2013 rankings of the world's 100 most valuable brands published by Millward Brown Optimor showed the company's brand value at number 61.Intel has also begun research into electrical transmission and generation. Intel has recently introduced a 3-D transistor that improves performance and energy efficiency. Intel has begun mass-producing this 3-D transistor, named the Tri-Gate transistor, with their 22 nm process, which is currently used in their 3rd generation core processors initially released on April 29, 2012. In 2011, SpectraWatt Inc., a solar cell spinoff of Intel, filed for bankruptcy under Chapter 11. In June 2013, Intel unveiled its fourth generation of Intel Core processors in an event named Computex in Taipei.The Open Source Technology Center at Intel hosts PowerTOP and LatencyTOP, and supports other open-source projects such as Wayland, Intel Array Building Blocks, Threading Building Blocks , and Xen. Wikipedia.

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3D NAND memory structures and related method are provided. In some embodiments such structures can include a control gate material and a floating gate material disposed between a first insulating layer and a second insulating layer, an interpoly dielectric (IPD) layer disposed between the floating gate material and control gate material such that the IPD layer electrically isolates the control gate material from the floating gate material, and a tunnel dielectric material deposited on the floating gate material opposite the control gate material.


Patent
Intel Corporation | Date: 2017-03-15

Technology for performing device-to-device (D2D) communications is disclosed. A user equipment (UE) can identify D2D data to be transmitted from the UE. The D2D data can be identified when the UE is in a radio resource control (RRC) idle. The UE can be limited to using a defined resource allocation mode to transmit the D2D data from the UE. A service request procedure can be initiated at the UE. The service request procedure can trigger the UE to perform an RRC connection establishment procedure with an evolved node B (eNB) to switch the UE from the RRC idle mode to an RRC connected mode. The UE can receive an uplink (UL) grant from the eNB for communicating the D2D data from the UE. The UE can send the D2D data using the UL grant provided by the eNB.


Patent
Intel Corporation | Date: 2017-02-01

The present disclosure provides techniques for a flexible sensor. In particular, the present disclosure provides techniques for a flexible, capacitive flexible sensor. A computing device can include a flexible sensor to collect input. The computing device can also include a processor to process the input. A deformation of the flexible sensor changes a capacitance of the flexible sensor.


Patent
Intel Corporation | Date: 2017-01-11

The present application is directed to dynamic reassignment for multi-OS devices. An example device may comprise equipment, at least two operating systems, a kernel for each OS to provide an interface between the OS and the equipment and a virtual machine manager (VMM). OS selection agents in each OS may interact with a kernel mode controller (KMC) in the VMM. For example, the OS selection agent may transmit a message instructing the KMC to transition the foreground OS to the background and transition a background OS to the foreground. The KMC may transmit signals to the kernels of the foreground and background operating systems causing at least one driver in the foreground OS kernel to save a current equipment state and release control over the equipment while also causing at least one driver in the background OS kernel to restore an equipment state and to take control over the equipment.


Patent
Intel Corporation | Date: 2017-01-25

Various embodiments are generally directed to an apparatus, method and other techniques for receiving information to invoke a transition from a first operating system to a second operating system, copying a system context for the second operating system from a location of a non-volatile memory to a volatile memory, the location associated with the second operating system and transitioning from the first operating system to the second operating system using the system context for the second operating system.


An Evolved Node-B (eNB) to communicate with a User Equipment (UE) on a Long Term Evolution (LTE) network, the eNB comprising: a first logic to determine whether a UE is capable of receiving and transmitting data at substantially the same time or receiving data at two different frequencies at the same time; and a second logic to configure for the UE a Discontinuous Reception (DRX) configuration such that a DRX ON duration overlaps with a discovery opportunity duration (DOD) according to the determination from the first logic.


Patent
Intel Corporation | Date: 2017-04-19

Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a layout for a metallization layer of an integrated circuit includes a first region having a plurality of unidirectional lines of a first width and a first pitch and parallel with a first direction. The layout also includes a second region having a plurality of unidirectional lines of a second width and a second pitch and parallel with the first direction, the second width and the second pitch different than the first width and the first pitch, respectively. The layout also includes a third region having a plurality of unidirectional lines of a third width and a third pitch and parallel with the first direction, the third width and the third pitch different than the first and second widths and different than the first and second pitches.


Patent
Intel Corporation | Date: 2017-02-08

In one example an inertial measurement unit comprises an autocalibration module to compute a covariance matrix from data received from a plurality of sensors, an adaptive weight control module to determine state-based feedback parameters for the gyroscope sensor,accelerometer sensor, and magnetometer sensor,and a sensor characteristic adjustment module to determine a modified covariance matrix based on an input from the adaptive weight control module. Other examples may be described.


Patent
Intel Corporation | Date: 2017-01-04

Examples may include techniques for allocating configurable computing resources from a pool of configurable computing resources to a logical server or virtual machine. The logical server or virtual machine may use allocated configurable computing resources to implement, execute or run a workload.


A processor includes logic to fetch an instruction stream divided into a plurality of strands for loading on one or more execution ports, identify a plurality of pending instructions, determine which of the strands are active, determine a program order of each of the pending instructions, and match the pending instructions to the execution ports based upon the program order of each pending instruction and whether each strand is active. Each pending instruction is at a respective head of one of the strands.

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