Santa Clara, CA, United States

Intel Corporation

www.intel.com
Santa Clara, CA, United States

Intel Corporation is an American multinational corporation headquartered in Santa Clara, California. Intel is one of the world's largest and highest valued semiconductor chip makers, based on revenue. It is the inventor of the x86 series of microprocessors, the processors found in most personal computers.Intel Corporation, founded on July 18, 1968, is a portmanteau of Integrated Electronics . Intel also makes motherboard chipsets, network interface controllers and integrated circuits, flash memory, graphic chips, embedded processors and other devices related to communications and computing. Founded by semiconductor pioneers Robert Noyce and Gordon Moore and widely associated with the executive leadership and vision of Andrew Grove, Intel combines advanced chip design capability with a leading-edge manufacturing capability. Though Intel was originally known primarily to engineers and technologists, its "Intel Inside" advertising campaign of the 1990s made it a household name, along with its Pentium processors.Intel was an early developer of SRAM and DRAM memory chips, and this represented the majority of its business until 1981. Although Intel created the world's first commercial microprocessor chip in 1971, it was not until the success of the personal computer that this became its primary business. During the 1990s, Intel invested heavily in new microprocessor designs fostering the rapid growth of the computer industry. During this period Intel became the dominant supplier of microprocessors for PCs, and was known for aggressive and sometimes illegal tactics in defense of its market position, particularly against Advanced Micro Devices , as well as a struggle with Microsoft for control over the direction of the PC industry.The 2013 rankings of the world's 100 most valuable brands published by Millward Brown Optimor showed the company's brand value at number 61.Intel has also begun research into electrical transmission and generation. Intel has recently introduced a 3-D transistor that improves performance and energy efficiency. Intel has begun mass-producing this 3-D transistor, named the Tri-Gate transistor, with their 22 nm process, which is currently used in their 3rd generation core processors initially released on April 29, 2012. In 2011, SpectraWatt Inc., a solar cell spinoff of Intel, filed for bankruptcy under Chapter 11. In June 2013, Intel unveiled its fourth generation of Intel Core processors in an event named Computex in Taipei.The Open Source Technology Center at Intel hosts PowerTOP and LatencyTOP, and supports other open-source projects such as Wayland, Intel Array Building Blocks, Threading Building Blocks , and Xen. Wikipedia.

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Time filter
Source Type

A circuit (10) is configured to reduce a noise component of a measured phase signal. The circuit (10) comprises an input (12) for a phase signal of an oscillator and an error signal estimator (14) configured to determine parity information and an estimated error amplitude in the phase signal based on the parity information. The circuit (20) further comprises a combiner (16) configured to provide the measured phase signal with the reduced noise component based on a combination of the phase signal and the estimated error amplitude.


Patent
Intel Corporation | Date: 2017-09-13

The present disclosure relates to methods and apparatuses for compensating carrier or clock signal phase fluctuations. An apparatus comprises a digital phase locked loop (210) comprising a phase error output (214) for a phase error (216) between a reference signal (218) and an output signal (212) generated by the digital phase locked loop, and a phase rotator (220) coupled to the phase error output (214) and configured to rotate a phase of a data signal based on the phase error (216).


Technology for periodic channel state information (CSI) reporting in a coordinated multipoint (CoMP) scenario is disclosed. One method can include a user equipment (UE) generating a plurality of CSI reports for transmission in a subframe for a plurality of CSI processes. Each CSI report can correspond to a CSI process with a CSIProcessIndex. The UE can drop CSI reports corresponding to CSI processes except a CSI process with a lowest CSIProcesslndex. The UE can transmit at least one CSI report for the CSI process to an evolved Node B (eNB).


Patent
Intel Corporation | Date: 2017-09-20

Embodiments of techniques and systems for sharing user information between proximate devices are described. In embodiments, a first device may identify a physically-proximate device that may receive user information. Upon receiving an indication that a user of the first device may desire to share user information with a user of the second device, a determination may be made as to whether the two users have matching interests. In embodiments, the interest match determination may be made by a separate interest match evaluator. Upon determination of an interest match, the first device may then send a request to share user information to the second device. If a user of the second device approves the request, user information for the user of the first device may be shared with the user of the second device. Other embodiments may be described and claimed.


A user equipment (UE) includes a transmission mode component, a selection component, and a transmission component. The transmission mode component is configured to selectively allocate resources for device-to-device communication according to a plurality of transmission modes. The plurality of transmission modes include a first transmission mode in which the resources used by the UE are specifically allocated by one of a base station or relay node and a second transmission mode in which the UE selects the resources from a pool of available resources. The selection component is configured to select a selected transmission mode. The transmission component is configured to transmit signals in frequency resources selected according to the selected transmission mode.


Patent
Intel Corporation | Date: 2017-09-13

Techniques are disclosed for processing a video stream to reduce platform power by employing a stepped and distributed pipeline process, wherein CPU-intensive processing is selectively performed. The techniques are particularly well-suited for hand-based navigational gesture processing. In one example case, for instance, the techniques are implemented in a computer system wherein initial threshold detection (image disturbance) and optionally user presence (hand image) processing components are proximate to or within the systems camera, and the camera is located in or proximate to the systems primary display. In some cases, image processing and communication of pixel information between various processing stages which lies outside a markered region is suppressed. In some embodiments, the markered region is aligned with, a mouse pad or designated desk area or a user input device such as a keyboard. Pixels evaluated by the system can be limited to a subset of the markered region.


Patent
Intel Corporation | Date: 2017-09-20

A hand held device containing at least one camera can perform various functions. In some embodiments, digitized images taken with two or more camera lenses having different fixed focal lengths may be combined to emulate a high-resolution optical zoom, and may also permit the device to perform 3D applications. In other embodiments, a device containing a camera may perform as a bar code reader, and may wirelessly transmit and/or visually present a bar code to other devices. Movable optics may permit the same camera to focus on either distant objects or on a close-up bar code.


A synthesis device (200) for generating a set of dynamic channel estimation (CE) filter coefficients (207) for a user equipment includes: a synthesis parameter generator (201), configured to generate a set of quasi-static synthesis parameters (202) from a reference symbol (RS) time-frequency pattern (300) and a set of slowly changing channel parameters (216), wherein the set of quasi-static synthesis parameters (202) is derived from a channel autocorrelation matrix (R) and at least one cross-correlation vector (r), and the set of slowly changing channel parameters (216) are derived from delay and Doppler power profiles (210) of a physical channel; a memory (203) configured to store the set of quasi-static synthesis parameters (202); and a CE filter coefficient generator (205), configured to generate a set of dynamic CE filter coefficients (w, 207) based on the set of quasi-static synthesis parameters (202), and a set of dynamic parameters (218) given by a cross modulation (D, 214) between RS signals from different cells (c) with cell-specific modulations, and a noise and interference SINR autocorrelation (, 212).


Patent
Intel Corporation | Date: 2017-09-20

A receptacle which is communicatively coupled to a host computing device and a method of receiving a plug at a receptacle are disclosed. The plug is received at the receptacle, the receptacle including contacts disposed with a rotational symmetry about a center point of the receptacle. Any orientation of the plug inserted into the receptacle is determined via detection circuitry. A connection path coupled to the contacts is changed via selection control circuitry, based on the orientation of the plug.


Eliazar I.,Intel Corporation
Physics Reports | Year: 2016

Living in the era of “big-data” information, we are ubiquitously inundated by overabundances of sizes—non-negative numerical values representing count, score, length, area, volume, duration, mass, energy, etc. Datasets of sizes display numerous types of statistical variability that are commonly quantified either by the standard deviation, or by the Boltzmann-Gibbs-Shannon entropy. The standard deviation measures the sizes’ Euclidean divergence from their mean, the Boltzmann-Gibbs-Shannon entropy measures the sizes’ informational divergence from the benchmark of pure determinism, and both these gauges are one-dimensional. In this paper we overview a methodology that harnesses inequality in order to quantify statistical variability. The methodology follows a socioeconomic approach of measuring the sizes’ inequality-their divergence from the benchmark of pure egalitarianism-and yields frameworks that gauge statistical variability in a multi-dimensional fashion. The aim of this overview is to serve both researchers and practitioners as a crash-introduction to the “harnessing inequality” methodology, and as a crash-manual to the implementation of this methodology. © 2016 Elsevier B.V.

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