Microelectronics Institute of Seville

Sevilla, Spain

Microelectronics Institute of Seville

Sevilla, Spain
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Sanchez-Lopez C.,Autonomous University of Tlaxcala | Sanchez-Lopez C.,Microelectronics Institute of Seville | Sanchez-Lopez C.,University of Seville | Trejo-Guerra R.,National Institute of Astrophysics, Optics and Electronics | And 2 more authors.
Nonlinear Dynamics | Year: 2010

The generation of n-scroll chaotic attractors by using saturated nonlinear function series (SNFS) realized with positive-type second generation current conveyors (CCII+s), is introduced. The nonlinear dynamical system is expressed by a third-order differential equation and to carry out numerical simulations, SNFS are ideally modeled by using staircase functions. Therefore, numerical simulations are introduced to approximate the swings, widths, breakpoints and equilibrium points of the n-scroll attractors by considering, as input variables: the dynamic range associated to active devices, gain of the nonlinear system and the number of scrolls. Therefore, its dynamical behavior is investigated in the state space. Besides, the CCII± is a versatile analog building block and it has been demonstrated to be very useful in several linear and nonlinear applications, since CCII-based implementations offer better performances that Opamps-based implementations in terms of accuracy and bandwidth. Therefore, the nonlinear system is synthesized with CCII+s to generate 3- and 4-scrolls. HSPICE simulations and experimental results are shown to verify the agreement on the behavior of the proposed circuit and the numerical simulations. © 2010 Springer Science+Business Media B.V.

Martinez-Rodriguez M.C.,University of Seville | Martinez-Rodriguez M.C.,Microelectronics Institute of Seville | Brox P.,Microelectronics Institute of Seville | Castro J.,University of Seville | And 7 more authors.
2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012 | Year: 2012

This paper exposes a hardware-in-the-loop methodology to verify the performance of a programmable and configurable application specific integrated circuit (ASIC) that implements piecewise affine (PWA) controllers. The ASIC inserted into a printed circuit board (PCB) is connected to a logic analyzer that generates the input patterns to the ASIC (in particular, the values to program the memories, configuration parameters, and values of the input signals). The output provided by the ASIC is also taken by the logic analyzer. A Matlab program controls the logic analyzer to verify the PWA controller implemented by the ASIC in open-loop as well as in closed-loop configurations. © 2012 IEEE.

Baturone I.,University of Seville | Baturone I.,Microelectronics Institute of Seville | Martinez-Rodriguez M.C.,University of Seville | Martinez-Rodriguez M.C.,Microelectronics Institute of Seville | And 3 more authors.
Proceedings - ISIE 2011: 2011 IEEE International Symposium on Industrial Electronics | Year: 2011

This paper proposes the design of hierarchical piecewise-affine (PWA) controllers to alleviate the processing time or prohibitive memory requirements of large controller structures. The constituent PWA modules of the hierarchical solution have fewer inputs and/or coarser partitions, so that they can reduce considerably the hardware resources required and/or the time response of the controller. A design methodology aided by CAD tools is employed to design the parameters of the controller, implement its architecture in an FPGA, and verify the static and dynamic behavior of the digital implementation by applying hardware-in-the-loop testing. © 2011 IEEE.

Brox M.,University of Cordoba, Spain | Sanchez-Solano S.,Microelectronics Institute of Seville | Delgado L.,University of Seville
International Conference on Intelligent Systems Design and Applications, ISDA | Year: 2011

This paper presents a design technique that allows the automatic synthesis of fuzzy inference systems and accelerates the exploration of the design space of these systems. It is based on generic VHDL code generation which can be implemented on a programmable device (FPGA) or an application specific integrated circuit (ASIC). The set of CAD tools supporting this technique includes a specific environment for designing fuzzy systems, in combination with commercial VHDL simulation and synthesis tools. As demonstrated by the analyzed design examples, the described development strategy speeds up the stages of description, synthesis, and functional verification of fuzzy inference systems. © 2011 IEEE.

Sanchez-Lopez C.,UAT Apizaco | Mendoza-Lopez J.,Microelectronics Institute of Seville | Muniz-Montero C.,UPPUE Cuanala | Sanchez-Gaspariano L.A.,UPPUE Cuanala | Munoz-Pacheco J.M.,BUAP
2013 IEEE 4th Latin American Symposium on Circuits and Systems, LASCAS 2013 - Conference Proceedings | Year: 2013

In this paper, the trade-off between accuracy and simulation speed in the generation of muti-scroll chaotic attractors at 1-D is analyzed and improved. In a first step, a macromodel based on bipolar transistors and passive elements is used to model the behavior of Opamps, and later on they are used to approach the behavior of all nonlinear system. Hspice simulations are executed to generate chaotic attractors in the phase plane and time-series. CPU-time used during the solution of the chaotic system is computed. In a second stage, a simple and accurate nonlinear model, which includes the most influential performance parameters for Opamps, is coded in C++ and it is used to generate a nonlinear system of equations, which models the behavior of all chaotic system. CPU-time is also computed. Because chaotic waveforms generated have a random behavior, statistical tests are used to measure the similitude/accuracy between two random variables during a long time. Our results indicate that chaotic waveforms can swiftly be generated by using the simple but accurate model for Opamps without the accuracy worsens, independently of the initial conditions of the chaotic system. © 2013 IEEE.

Zhao B.,Agency for Science, Technology and Research Singapore | Ding R.,Nanyang Technological University | Chen S.,Nanyang Technological University | Linares-Barranco B.,Microelectronics Institute of Seville | Tang H.,Agency for Science, Technology and Research Singapore
IEEE Transactions on Neural Networks and Learning Systems | Year: 2015

This paper introduces an event-driven feedforward categorization system, which takes data from a temporal contrast address event representation (AER) sensor. The proposed system extracts bio-inspired cortex-like features and discriminates different patterns using an AER based tempotron classifier (a network of leaky integrate-and-fire spiking neurons). One of the system's most appealing characteristics is its event-driven processing, with both input and features taking the form of address events (spikes). The system was evaluated on an AER posture dataset and compared with two recently developed bio-inspired models. Experimental results have shown that it consumes much less simulation time while still maintaining comparable performance. In addition, experiments on the Mixed National Institute of Standards and Technology (MNIST) image dataset have demonstrated that the proposed system can work not only on raw AER data but also on images (with a preprocessing step to convert images into AER events) and that it can maintain competitive accuracy even when noise is added. The system was further evaluated on the MNIST dynamic vision sensor dataset (in which data is recorded using an AER dynamic vision sensor), with testing accuracy of 88.14%. © 2012 IEEE.

Tena E.,Microelectronics Institute of Seville | Castro J.,Microelectronics Institute of Seville | Acosta A.J.,Microelectronics Institute of Seville
19th IMEKO TC4 Symposium - Measurements of Electrical Quantities 2013 and 17th International Workshop on ADC and DAC Modelling and Testing | Year: 2013

This paper presents a methodology to perform automatic and systematic characterization test on application specific integrated circuits (ASICs). The proposed methodology is based on the automatic control of all laboratory equipment and the data processing with Matlab. The ASIC, or integrated system, is connected to controllable test equipment to generate patterns and collect the output data provided by the ASIC. The methodology that provides the Matlab script controlling the equipment, test process, making the analysis of the results and supervising the whole process, can be easily adapted to different experiments and ASIC features. The test of a piecewise affine (PWA) ASIC controller has been used to experimentally prove the automatic control in both open-loop as well as in closed-loop configurations, reducing the risk of manual measurement errors.

Sanchez-Lopez C.,Autonomous University of Tlaxcala | Mendoza-Lopez J.,Microelectronics Institute of Seville | Carrasco-Aguilar M.A.,Autonomous University of Tlaxcala | Morales-Lopez F.E.,Autonomous University of Tlaxcala
2013 10th International Conference on Electrical Engineering, Computing Science and Automatic Control, CCE 2013 | Year: 2013

The main purposes of this paper is to introduce a new floating memristor emulator circuit based on positive second generation current conveyors (CCII+s). The proposed circuit is very simple, since four CCII+s, six passive elements along with one four quadrant multiplier are only used to obtain the frequency-dependent pinched hysteresis loop of the memristor in the current versus voltage plane. An analysis on the frequency behavior of the memristor is also introduced, showing that the hysteresis loop is maintained up to 20 kHz. Numerical simulations along with experimental results are given to describe the dynamic behavior of the proposed circuit. Experimental results are in agreement with the theoretical analysis and numerical simulations. © 2013 IEEE.

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