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Smolinski L.,Institute of Computer Engineering and Electronics
Proceedings of IEEE East-West Design and Test Symposium, EWDTS'2011 | Year: 2011

Article presents modification for the cryptographic hardware accelerators. Modification, which allows for add new functionality to cryptography systems. Functionality allows for the dynamic changes in the number of rounds with maintaining uniformity in the processes of encryption and decryption. The proposed modification was discussed on DES algorithm example. © 2011 IEEE.


Titarenko L.,Institute of Computer Engineering and Electronics | Hebda O.,Institute of Computer Engineering and Electronics
Proceedings of IEEE East-West Design and Test Symposium, EWDTS 2013 | Year: 2013

The method is proposed for reduction of hardware amount in logic circuit of Moore finite state machine. The method is oriented on customized matrix technology. It is based on representation of the next state code as a concatenation of codes for class of pseudoequivalent states and collection of microoperations. Such an approach allows elimination of dependence among states and microoperations. As a result, both circuits for generation of input memory functions and microoperations are optimized. An example of the proposed method application is given. © 2013 IEEE.


Barkalov A.,Institute of Computer Engineering and Electronics | Titarenko L.,Institute of Computer Engineering and Electronics | Hebda O.,Institute of Computer Engineering and Electronics
Proceedings of IEEE East-West Design and Test Symposium, EWDTS'2011 | Year: 2011

The method is proposed for reduction of the area of matrix implementation of the circuit of the Moore finite state machine (FSM). The method is based on optimal state coding and decomposition of a matrix of terms on two sub-matrixes. Thus classes of the pseudoequivalent states are used. Such approach allows to reduce number of lines of the table of transitions of Moore FSM up to this value of the equivalent Mealy FSM. As a result the area of the matrixes forming excitation function of a states memory register is optimized. An example of the proposed method application is given. © 2011 IEEE.


Barkalov A.,Institute of Computer Engineering and Electronics | Titarenko L.,Institute of Computer Engineering and Electronics | Smolinski L.,Institute of Computer Engineering and Electronics
Proceedings of IEEE East-West Design and Test Symposium, EWDTS'2011 | Year: 2011

The method of hardware reduction is proposed which is oriented on compositional microprogram control units with code sharing and PAL-based CPLD chips. The method is based on a wide fan-in of PAL macrocells allowing using more than one source for codes of operational linear chains. An example of the proposed method application is given. © 2011 IEEE.


Barkalov A.,Institute of Computer Engineering and Electronics | Titarenko L.,Institute of Computer Engineering and Electronics | Smolinski L.,Institute of Computer Engineering and Electronics
Proceedings of IEEE East-West Design and Test Symposium, EWDTS 2013 | Year: 2013

The method of hardware reduction is proposed which is dedicated for compositional microprogram control unit implemented in CPLD. The method is based on using more than one data source in calculation of microinstruction address. Such approach permits to the decrease the number of logic blocks used for the implementation of the controller in the target CPLD. The paper presents the conditions needed to apply the method. An example of the proposed method application is given. © 2013 IEEE.

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