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Yeh B.-L.,Institute of Electro Optical Science and Engineering | Chen Y.-H.,Institute of Electro Optical Science and Engineering | Chiu L.-Y.,Institute of Electro Optical Science and Engineering | Lin J.-W.,Institute of Electro Optical Science and Engineering | And 6 more authors.
Journal of the Electrochemical Society | Year: 2011

We demonstrate a simple and an inexpensive approach for the low-temperature fabrication (<200°C) of low-voltage-operated (<20 V), organic, pentacene-based, nonvolatile memory devices with a high- k hafnium dioxide (Hf O2) main dielectric layer and a polymer electret layer. Two kinds of polymer insulators were used as the electret layer, i.e., a poly(vinylalcohol) (PVA) with strong polar groups and an amorphous poly(methyl methacrylate) (PMMA). We studied the memory characteristics of the corresponding devices, including writing and erasing process, long-term retention, and multiple continuous writing/erasing cycles' endurance testing. The memory windows in devices with PVA can be attributed to the dominant short-lifetime shallow traps located at the PVA/pentacene interface and in the pentacene film, whereas those in devices with PMMA are mainly due to the long-lifetime deep traps located in the PMMA layer. The possible sources of shallow-type and deep-type traps in the memory devices were discussed. Accordingly, the devices with the PMMA layer show superior memory characteristics, including a stable memory window of approximately 2.5 V after 20 V 1 s pulse, retaining 80% of memory windows after 103 s and a good endurance properties. © 2011 The Electrochemical Society.


Huang Y.-T.,National Cheng Kung University | Wu S.-L.,Cheng Shiu University | Chang S.-J.,Institute of Electro Optical Science and Engineering | Kuo C.-W.,National Cheng Kung University | And 3 more authors.
IEEE Transactions on Nanotechnology | Year: 2011

Implementation of strained-Si MOSFETs with optimum low-cost stress-memorization technique for a 40-nm technology CMOS process was demonstrated. Devices fabricated on (100) substrate with 100channel orientation provide additional 8% current drivability improvement for strained-Si nMOSFETs without any degradation of pMOSFETs performance. The stress-memorization technique (SMT) mechanism was experimentally verified by studying the impact of layout geometry (length of source/drain LS/D and polyspacing) on the device performance. In the SMT devices with LS/D down to 0.11 m and polyspace reduced to 120 nm, no obvious current improvement and more performance degradation are observed compared with control device (only strained contact etch-stop layer), indicating that the benefit of the SMT is substantially eliminated and showing that the SMT-induced stress is mainly originated from the source/drain region in our case. © 2010 IEEE.


Huang Y.-H.,National Cheng Kung University | Ko S.-W.,National Cheng Kung University | Fuh A.Y.-G.,Institute of Electro Optical Science and Engineering
Proceedings of the International Display Workshops | Year: 2012

This paper demonstrated the research of axially symmetric dye-doped liquid crystal (ASDDLC). Axially symmetric devices were widely used in symmetric optics, such as converting linear polarized light into axially, azimuthally or vortically light. The novel applications have been presented, such as polarization-independent liquid crystal lens and tunable donut beam.


Ho T.-Y.,Institute of Electro Optical Science and Engineering | Lee C.-Y.,Institute of Electro Optical Science and Engineering | Kuo C.-W.,National Cheng Kung University | Tang F.-C.,National Cheng Kung University | And 3 more authors.
Electrochemical and Solid-State Letters | Year: 2010

We demonstrate a plasma-beam-processed polyimide (PI) surface to effectively align liquid crystal (LC) molecules. The pretilt angles of LCs can be varied between 0 and 3.5°, and the PI surface energy can be adjusted by controlling the plasma beam with an energy of 450 eV at an incident angle varying from 0 to 80° with respect to the normal direction of the substrate. Additionally, a method was developed to quickly evaluate the level of anchoring force of LC when compared with a rubbed-aligned LC cell. The performance of this method should be under LC cells with the same alignment materials. © 2010 The Electrochemical Society.

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