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Serrano-Gotarredona T.,Institute Microelectronica Of Seville Imsecnm Csic | Linares-Barranco B.,Institute Microelectronica Of Seville Imsecnm Csic
IEEE Journal of Solid-State Circuits | Year: 2013

Dynamic Vision Sensors (DVS) have recently appeared as a new paradigm for vision sensing and processing. They feature unique characteristics such as contrast coding under wide illumination variation, micro-second latency response to fast stimuli, and low output data rates (which greatly improves the efficiency of post-processing stages). They can track extremely fast objects (e.g., time resolution is better than 100 kFrames/s video) without special lighting conditions. Their availability has triggered a new range of vision applications in the fields of surveillance, motion analyses, robotics, and microscopic dynamic observations. One key DVS feature is contrast sensitivity, which has so far been reported to be in the 10-15% range. In this paper, a novel pixel photo sensing and transimpedance pre-amplification stage makes it possible to improve by one order of magnitude contrast sensitivity (down to 1.5%) and power (down to 4 mW), reduce the best reported FPN (Fixed Pattern Noise) by a factor of 2 (down to 0.9%), while maintaining the shortest reported latency (3 μs) and good Dynamic Range (120 dB), and further reducing overall area (down to 30×,31 μm 2 per pixel). The only penalty is the limitation of intrascene Dynamic Range to 3 decades. A 128,× 128 DVS test prototype has been fabricated in standard 0.35 μm CMOS and extensive experimental characterization results are provided. © 1966-2012 IEEE. Source


Zamarreno-Ramos C.,Institute Microelectronica Of Seville Imsecnm Csic | Serrano-Gotarredona T.,Institute Microelectronica Of Seville Imsecnm Csic | Linares-Barranco B.,Institute Microelectronica Of Seville Imsecnm Csic
IEEE Transactions on Circuits and Systems I: Regular Papers | Year: 2011

This paper presents a serializer/deserializer scheme for asynchronous address event representation (AER) bit-serial interchip communications. Each serial AER (sAER) link uses four wires: a micro strip pair for low voltage differential signaling (LVDS) and two handshaking lines. Each event is represented by a 32-bit word. Two extra preamble bits are used for alignment. Transmission clock is embedded in the data using Manchester encoding. As opposed to conventional LVDS links, the presented approach allows to stop physical communication between data events, so that no comma characters need to be transmitted during these pauses. As soon as a new event needs to be transmitted, the link recovers immediately thanks to a built-in control voltage memorization circuit. As a result, power consumption of the serializer and deserializer circuits is proportional to data event rate. The approach is also highly tolerant to clock jitter, due to the asynchronous nature and the Manchester encoding. A chip test prototype has been fabricated in standard 0.35 μm CMOS including a pair of Serializer and Deserializer circuits. Maximum measured event transmission rate is 15 Meps (mega events per second) for 32-bit events, with a maximum bit transmission speed of 670 Mbps (mega bits per second). © 2011 IEEE. Source


Nunez J.,Institute Microelectronica Of Seville Imsecnm Csic | Nunez J.,University of Seville | Avedillo M.J.,Institute Microelectronica Of Seville Imsecnm Csic | Avedillo M.J.,University of Seville | And 2 more authors.
IEEE Transactions on Nanotechnology | Year: 2011

The incorporation of resonant tunneling diodes (RTDs) into III/V transistor technologies has shown an improved circuit performance, producing higher circuit speed, reduced component count, and/or lower power consumption. Currently, the incorporation of these devices into CMOS technologies (RTD-CMOS) is an area of active research. Although some studies have concentrated on evaluating the advantages of this incorporation, more work in this direction is required. In this letter, we compare RTD-CMOS and pure CMOS realizations of a logic gate network which can be operated in a gate-level pipeline. Significantly lower average power is obtained for RTD-CMOS implementations. © 2011 IEEE. Source


Camunas-Mesa L.,Institute Microelectronica Of Seville Imsecnm Csic | Acosta-Jimenez A.,Institute Microelectronica Of Seville Imsecnm Csic | Zamarreno-Ramos C.,Institute Microelectronica Of Seville Imsecnm Csic | Serrano-Gotarredona T.,Institute Microelectronica Of Seville Imsecnm Csic | Linares-Barranco B.,Institute Microelectronica Of Seville Imsecnm Csic
IEEE Transactions on Circuits and Systems I: Regular Papers | Year: 2011

This paper describes a convolution chip for event-driven vision sensing and processing systems. As opposed to conventional frame-constraint vision systems, in event-driven vision there is no need for frames. In frame-free event-based vision, information is represented by a continuous flow of self-timed asynchronous events. Such events can be processed on the fly by event-based convolution chips, providing at their output a continuous event flow representing the 2-D filtered version of the input flow. In this paper we present a 32 × 32 pixel 2-D convolution event processor whose kernel can have arbitrary shape and size up to 32 × 32. Arrays of such chips can be assembled to process larger pixel arrays. Event latency between input and output event flows can be as low as 155 ns. Input event throughput can reach 20 Meps (mega events per second), and output peak event rate can reach 45 Meps. The chip can be configured to discriminate between two simulated propeller-like shapes rotating simultaneously in the field of view at a speed as high as 9400 rps (revolutions per second). Achieving this with a frame-constraint system would require a sensing and processing capability of about 100 K frames per second. The prototype chip has been built in 0.35 μm CMOS technology, occupies 4.3 × 5.4 mm2 and consumes a peak power of 200 mW at maximum kernel size at maximum input event rate. © 2010 IEEE. Source

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