Institute Microelectronica Of Seville Imse Cnm Csic

Sevilla, Spain

Institute Microelectronica Of Seville Imse Cnm Csic

Sevilla, Spain

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Brox P.,Institute Microelectronica Of Seville Imse Cnm Csic | Baturone I.,Institute Microelectronica Of Seville Imse Cnm Csic | Baturone I.,University of Seville | Sanchez-Solano S.,Institute Microelectronica Of Seville Imse Cnm Csic
Applied Soft Computing Journal | Year: 2014

Video de-interlacing algorithms perform a crucial task in video processing. Despite these algorithms are developed using software implementations, their implementations in hardware are required to achieve real-time operation. This paper describes the development of an embedded system for video de-interlacing. The algorithm for video de-interlacing uses three fuzzy logic-based systems to tackle three relevant features in video sequences: motion, edges, and picture repetition. The proposed strategy implements the algorithm as a hardware IP core on a FPGA-based embedded system. The paper details the proposed architecture and the design methodology to develop it. The resulting embedded system is verified on a FPGA development board and it is able to de-interlace in real-time. © 2013 Elsevier B.V. All rights reserved.


Perez-Carrasco J.A.,Institute Microelectronica Of Seville Imse Cnm Csic | Perez-Carrasco J.A.,University of Seville | Serrano C.,University of Seville | Acha B.,University of Seville | And 2 more authors.
Proceedings - International Conference on Pattern Recognition | Year: 2010

In this paper we propose the first bio-inspired six-layer convolutional network (ConvNet) non-frame based that can be implemented with already physically available spike-based electronic devices. The system was designed to recognize people in three different positions: standing, lying or up-side-down. The inputs were spikes obtained with a motion retina chip. We provide simulation results showing recognition delays of 16 milliseconds from stimulus onset (time-to-first spike) with a recognition rate of 94%. The weight sharing property in ConvNets and the use of AER protocol allow a great reduction in the number of both trainable parameters and connections (only 748 trainable parameters and 123 connections in our AER system (out of 506998 connections that would be required in a frame-based implementation). © 2010 IEEE.


Serrano-Gotarredona T.,Institute Microelectronica Of Seville Imse Cnm Csic | Park J.,University of California at San Diego | Linares-Barranco A.,University of Seville | Jimenez A.,University of Seville | And 2 more authors.
Proceedings - IEEE International Symposium on Circuits and Systems | Year: 2013

This paper presents a new DVS sensor with one order of magnitude improved contrast sensitivity over previous reported DVSs. This sensor has been applied to a bio-inspired event-based binocular system that performs 3D event-driven reconstruction of a scene. Events from two DVS sensors are matched by using precise timing information of their ocurrence. To improve matching reliability, satisfaction of epipolar geometry constraint is required, and simultaneously available information on the orientation is used as an additional matching constraint. © 2013 IEEE.


Moreno R.L.,Federal University of Itajubá | Vazquez D.,Institute Microelectronica Of Seville Imse Cnm Csic
IEEE Latin America Transactions | Year: 2016

This paper investigates the capability of an architecture with digitally controllable gain and power consumption, for mitigating the effects of process variations on CMOS Low-Noise Amplifiers (LNAs). A 130-nm 1.2-V LNA with the proposed architecture is designed, based on the analysis of variability in LNAs with a traditional architecture under different biasing currents conditions, and the corresponding effects in the performance of a complete receiver context. Two different adjusting strategies are evaluated, which could be implemented with already reported Built-in Self-Test (BIST) circuits. Results show that the proposed architecture allows yield enhancement with low-power operation compared to traditional LNAs. © 2003-2012 IEEE.


Sanchez-Solano S.,Institute Microelectronica Of Seville Imse Cnm Csic | Brox M.,University of Cordoba, Spain | del Toro E.,Microelectronics Research Center Israel | Brox P.,Institute Microelectronica Of Seville Imse Cnm Csic | Baturone I.,Instituto Demicroelectronica Of Seville Imse Cnmcsic
IEEE Transactions on Industrial Informatics | Year: 2013

The complexity reached by current applications of industrial control systems has motivated the development of new computational paradigms, as well as the employment of hybrid implementation techniques that combine hardware and software components to fulfill system requirements. On the other hand, continuous improvements in field-programmable devices today make possible the implementation of complex control systems on reconfigurable hardware, although they are limited by the lack of specific design tools and methodologies to facilitate the development of new products. This paper describes a model-based design approach for the synthesis of embedded fuzzy controllers on field-programmable gate arrays (FPGAs). Its main contributions are the proposal of a novel implementation technique, which allows accelerating the exploration of the design space of fuzzy inference modules, and the use of a design flow that eases their integration into complex control systems and the joint development of hardware and software components. This design flow is supported by specific tools for fuzzy systems development and standard FPGA synthesis and implementation tools, which use the modeling and simulation facilities provided by the Matlab environment. The development of a complex control system for parking an autonomous vehicle demonstrates the capabilities of the proposed procedure to dramatically speed up the stages of description, synthesis, and functional verification of embedded fuzzy controllers for industrial applications. © 2005-2012 IEEE.


Perez-Carrasco J.A.,Institute Microelectronica Of Seville Imse Cnm Csic | Zamarreno-Ramos C.,Institute Microelectronica Of Seville Imse Cnm Csic | Serrano-Gotarredona T.,Institute Microelectronica Of Seville Imse Cnm Csic | Linares-Barranco B.,Institute Microelectronica Of Seville Imse Cnm Csic
ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems | Year: 2010

Neuromorphic circuits and systems techniques have great potential for exploiting novel nanotechnology devices, which suffer from great parametric spread and high defect rate. In this paper we explore some potential ways of building neural network systems for sophisticated pattern recognition tasks using memristors. We will focus on spiking signal coding because of its energy and information coding efficiency, and concentrate on Convolutional Neural Networks because of their good scaling behavior, both in terms of number of synapses and temporal processing delay. We propose asynchronous architectures that exploit memristive synapses with specially designed neurons that allow for arbitrary scalability as well as STDP learning. We present some behavioral simulation results for small neural arrays using electrical circuit simulators, and system level spike processing results on human detection using a custom made event based simulator. ©2010 IEEE.


Lenero-Bardallo J.A.,Institute Microelectronica Of Seville Imse Cnm Csic | Serrano-Gotarredona T.,Institute Microelectronica Of Seville Imse Cnm Csic | Linares-Barranco B.,Institute Microelectronica Of Seville Imse Cnm Csic
ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems | Year: 2010

Reported AER (Address Event Representation) contrast retinae perform a contrast computation based on the ratio between a pixel's local light intensity and a spatially weighted average of its neighbourhood. This results in compact circuits, but with the penalty of all pixels generating output signals even if they sense no contrast. In this paper we present a spatial contrast retina with bipolar output: contrast is computed as the relative normalized difference (not the ratio) between a pixel's local light and its weighted spatial average, normalized to average light. As a result, contrast includes a sign, is ambient light independent, and the output will be zero if there is no contrast. Furthermore, an adjustable thresholding mechanism has been included, such that pixels remain silent until they sense an absolute contrast above the adjustable threshold. The pixel contrast computation circuit is based on Boahen's Biharmonic operator contrast circuit, which has been improved to include mismatch calibration and adaptive current based biasing. As a result, the contrast computation circuit shows much less mismatch, is almost insensitive to ambient light illumination, and biasing is much less critical than in the original voltage biasing scheme. The retina also includes an optional TFS (Time-to-First-Spike) integration mode. A full AER retina version has been fabricated and tested. In the present paper we provide preliminary experimental results. ©2010 IEEE.


Zamarreno-Ramos C.,Institute Microelectronica Of Seville Imse Cnm Csic | Linares-Barranco A.,Institute Microelectronica Of Seville Imse Cnm Csic | Serrano-Gotarredona T.,Institute Microelectronica Of Seville Imse Cnm Csic | Linares-Barranco B.,Institute Microelectronica Of Seville Imse Cnm Csic
IEEE Transactions on Biomedical Circuits and Systems | Year: 2013

This paper presents a modular, scalable approach to assembling hierarchically structured neuromorphic Address Event Representation (AER) systems. The method consists of arranging modules in a 2D mesh, each communicating bidirectionally with all four neighbors. Address events include a module label. Each module includes an AER router which decides how to route address events. Two routing approaches have been proposed, analyzed and tested, using either destination or source module labels. Our analyses reveal that depending on traffic conditions and network topologies either one or the other approach may result in better performance. Experimental results are given after testing the approach using high-end Virtex-6 FPGAs. The approach is proposed for both single and multiple FPGAs, in which case a special bidirectional parallel-serial AER link with flow control is exploited, using the FPGA Rocket-I/O interfaces. Extensive test results are provided exploiting convolution modules of 64\,\times\,64 pixels with kernels with sizes up to 11\,\times\, 11, which process real sensory data from a Dynamic Vision Sensor (DVS) retina. One single Virtex-6 FPGA can hold up to 64 of these convolution modules, which is equivalent to a neural network with 262 \times 10{3}~{\rm neurons} and almost 32 million synapses. © 2012 IEEE.


Perez-Carrasco J.A.,Polytechnic University of Valencia | Zhao B.,Nanyang Technological University | Serrano C.,Polytechnic University of Valencia | Acha B.,Polytechnic University of Valencia | And 3 more authors.
IEEE Transactions on Pattern Analysis and Machine Intelligence | Year: 2013

Event-driven visual sensors have attracted interest from a number of different research communities. They provide visual information in quite a different way from conventional video systems consisting of sequences of still images rendered at a given 'frame rate.' Event-driven vision sensors take inspiration from biology. Each pixel sends out an event (spike) when it senses something meaningful is happening, without any notion of a frame. A special type of event-driven sensor is the so-called dynamic vision sensor (DVS) where each pixel computes relative changes of light or 'temporal contrast.' The sensor output consists of a continuous flow of pixel events that represent the moving objects in the scene. Pixel events become available with microsecond delays with respect to 'reality.' These events can be processed 'as they flow' by a cascade of event (convolution) processors. As a result, input and output event flows are practically coincident in time, and objects can be recognized as soon as the sensor provides enough meaningful events. In this paper, we present a methodology for mapping from a properly trained neural network in a conventional frame-driven representation to an event-driven representation. The method is illustrated by studying event-driven convolutional neural networks (ConvNet) trained to recognize rotating human silhouettes or high speed poker card symbols. The event-driven ConvNet is fed with recordings obtained from a real DVS camera. The event-driven ConvNet is simulated with a dedicated event-driven simulator and consists of a number of event-driven processing modules, the characteristics of which are obtained from individually manufactured hardware modules. © 1979-2012 IEEE.


Camunas-Mesa L.,Institute Microelectronica Of Seville Imse Cnm Csic | Perez-Carrasco J.A.,Institute Microelectronica Of Seville Imse Cnm Csic | Zamarreno-Ramos C.,Institute Microelectronica Of Seville Imse Cnm Csic | Serrano-Gotarredona T.,Institute Microelectronica Of Seville Imse Cnm Csic | Linares-Barranco B.,Institute Microelectronica Of Seville Imse Cnm Csic
ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems | Year: 2010

This paper summarizes how Convolutional Neural Networks (ConvNets) can be implemented in hardware using Spiking neural network Address-Event- Representation (AER) technology, for sophisticated pattern and object recognition tasks operating at mili second delay throughputs. Although such hardware would require hundreds of individual convolutional modules and thus is presently not yet available, we discuss methods and technologies for implementing it in the near future. On the other hand, we provide precise behavioral simulations of large scale spiking AER convolutional hardware and evaluate its performance, by using peformance figures of already available AER convolution chips fed with real sensory data obtained from physically available AER motion retina chips. We provide simulation results of systems trained for people recognition, showing recognition delays of a few miliseconds from stimulus onset. ConvNets show good up scaling behavior and possibilities for being implemented efficiently with new nano scale hybrid CMOS/nonCMOS technologies. ©2010 IEEE.

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