Institute Microelectronica Of Seville

Sevilla, Spain

Institute Microelectronica Of Seville

Sevilla, Spain
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Farabet C.,Courant Institute of Mathematical Sciences | Farabet C.,University Paris Est Creteil | Paz R.,University of Seville | Perez-Carrasco J.,Institute Microelectronica Of Seville | And 6 more authors.
Frontiers in Neuroscience | Year: 2012

Most scene segmentation and categorization architectures for the extraction of features in images and patches make exhaustive use of 2D convolution operations for template matching, template search, and denoising. Convolutional Neural Networks (ConvNets) are one example of such architectures that can implement general-purpose bio-inspired vision systems. In standard digital computers 2D convolutions are usually expensive in terms of resource consumption and impose severe limitations for efficient real-time applications. Nevertheless, neuro-cortex inspired solutions, like dedicated Frame-Based or Frame-Free Spiking ConvNet Convolution Processors, are advancing real-time visual processing. These two approaches share the neural inspiration, but each of them solves the problem in different ways. Frame-Based ConvNets process frame by frame video information in a very robust and fast way that requires to use and share the available hardware resources (such as: multipliers, adders). Hardware resources are fixed- and time-multiplexed by fetching data in and out. Thus memory bandwidth and size is important for good performance. On the other hand, spike-based convolution processors are a frame-free alternative that is able to perform convolution of a spike-based source of visual information with very low latency, which makes ideal for very high-speed applications. However, hardware resources need to be available all the time and cannot be time-multiplexed. Thus, hardware should be modular, reconfigurable, and expansible. Hardware implementations in both VLSI custom integrated circuits (digital and analog) and FPGA have been already used to demonstrate the performance of these systems. In this paper we present a comparison study of these two neuro-inspired solutions. A brief description of both systems is presented and also discussions about their differences, pros and cons. © 2012 Farabet, Paz, Pérez-Carrasco, Zamarreño-Ramos, Linares- Barranco, LeCun, Culurciello, Serrano-Gotarredona and Linares-Barranco.

Perez-Carrasco J.A.,University of Seville | Perez-Carrasco J.A.,Institute Microelectronica Of Seville | Acha B.,University of Seville | Serrano C.,University of Seville | And 3 more authors.
IEEE Transactions on Neural Networks | Year: 2010

Address-event representation (AER) is an emergent hardware technology which shows a high potential for providing in the near future a solid technological substrate for emulating brain-like processing structures. When used for vision, AER sensors and processors are not restricted to capturing and processing still image frames, as in commercial frame-based video technology, but sense and process visual information in a pixel-level event-based frameless manner. As a result, vision processing is practically simultaneous to vision sensing, since there is no need to wait for sensing full frames. Also, only meaningful information is sensed, communicated, and processed. Of special interest for brain-like vision processing are some already reported AER convolutional chips, which have revealed a very high computational throughput as well as the possibility of assembling large convolutional neural networks in a modular fashion. It is expected that in a near future we may witness the appearance of large scale convolutional neural networks with hundreds or thousands of individual modules. In the meantime, some research is needed to investigate how to assemble and configure such large scale convolutional networks for specific applications. In this paper, we analyze AER spiking convolutional neural networks for texture recognition hardware applications. Based on the performance figures of already available individual AER convolution chips, we emulate large scale networks using a custom made event-based behavioral simulator. We have developed a new event-based processing architecture that emulates with AER hardware Manjunath's frame-based feature recognition software algorithm, and have analyzed its performance using our behavioral simulator. Recognition rate performance is not degraded. However, regarding speed, we show that recognition can be achieved before an equivalent frame is fully sensed and transmitted. © 2006 IEEE.

Lenero-Bardallo J.A.,University of Oslo | Serrano-Gotarredona T.,Institute Microelectronica Of Seville | Linares-Barranco B.,Institute Microelectronica Of Seville
IEEE Journal of Solid-State Circuits | Year: 2011

This paper presents a 128 × 128 dynamic vision sensor. Each pixel detects temporal changes in the local illumination. A minimum illumination temporal contrast of 10% can be detected. A compact preamplification stage has been introduced that allows to improve the minimum detectable contrast over previous designs, while at the same time reducing the pixel area by 1/3. The pixel responds to illumination changes in less than 3.6 μs. The ability of the sensor to capture very fast moving objects, rotating at 10 K revolutions per second, has been verified experimentally. A frame-based sensor capable to achieve this, would require at least 100 K frames per second. © 2011 IEEE.

Acasandrei L.,Institute Microelectronica Of Seville | Barriga A.,University of Seville
Proceedings - 16th IEEE International Conference on High Performance Computing and Communications, HPCC 2014, 11th IEEE International Conference on Embedded Software and Systems, ICESS 2014 and 6th International Symposium on Cyberspace Safety and Security, CSS 2014 | Year: 2014

In computer vision during the recent years a new paradigm for object detection has stimulated researchers and designers interest. The foundation of this new paradigm is the Local Binary Pattern (LBP) which is a nonparametric operator that efficiently extracts the features of local structures in images. This communication describes a software embedded implementation of LBP based algorithm for object detection, in particular targeting frontal face detection. © 2014 IEEE.

Acasandrei L.,Institute Microelectronica Of Seville | Barriga A.,University of Seville
IECON Proceedings (Industrial Electronics Conference) | Year: 2013

A design methodology to accelerate the face detection for embedded systems is described, starting from algorithm optimization (high level) and ending with software and hardware codesign (low level) by addressing the issues and the design decisions made at each level based on the performance measurements and system limitations. The implemented embedded face detection system consumes very little power compared with the traditional PC software implementations while maintaining the same detection accuracy. The proposed face detection acceleration methodology is suitable for real time applications. © 2013 IEEE.

Serrano-Gotarredona T.,Institute Microelectronica Of Seville | Masquelier T.,University Pompeu Fabra | Masquelier T.,University Pierre and Marie Curie | Prodromakis T.,Institute of Biomedical Engineering | And 2 more authors.
Frontiers in Neuroscience | Year: 2013

In this paper we review several ways of realizing asynchronous Spike-Timing-Dependent-Plasticity (STDP) using memristors as synapses. Our focus is on how to use individual memristors to implement synaptic weight multiplications, in a way such that it is not necessary to (a) introduce global synchronization and (b) to separate memristor learning phases from memristor performing phases. In the approaches described, neurons fire spikes asynchronously when they wish and memristive synapses perform computation and learn at their own pace, as it happens in biological neural systems. We distinguish between two different memristor physics, depending on whether they respond to the original "moving wall" or to the "filament creation and annihilation" models. Independent of the memristor physics, we discuss two different types of STDP rules that can be implemented with memristors: either the pure timing-based rule that takes into account the arrival time of the spikes from the pre- and the post-synaptic neurons, or a hybrid rule that takes into account only the timing of pre-synaptic spikes and the membrane potential and other state variables of the post-synaptic neuron. We show how to implement these rules in cross-bar architectures that comprise massive arrays of memristors, and we discuss applications for artificial vision. © 2013 Serrano-Gotarredona, Masquelier, Prodromakis, Indiveri and Linares-Barranco.

Fiorelli R.,Institute Microelectronica Of Seville | Peralias E.J.,Institute Microelectronica Of Seville | Silveira F.,University of the Republic of Uruguay
IEEE Transactions on Microwave Theory and Techniques | Year: 2011

In this paper, an LC voltage-controlled oscillator (LC-VCO) design optimization methodology based on the gm/ID technique and on the exploration of all inversion regions of the MOS transistor (MOST) is presented. An in-depth study of the compromises between phase noise and current consumption permits optimization of the design for given specifications. Semiempirical models of MOSTs and inductors, obtained by simulation, jointly with analytical phase noise models, allow to get a design space map where the design tradeoffs are easily identified. Four LC-VCO designs in different inversion regions in a 90-nm CMOS process are obtained with the proposed methodology and verified with electrical simulations. Finally, the implementation and measurements are presented for a 2.4-GHz VCO operating in moderate inversion. The designed VCO draws 440 μA from a 1.2-V power supply and presents a phase noise of -106.2 dBc/Hz at 400 kHz from the carrier. © 2011 IEEE.

Acasandrei L.,Institute Microelectronica Of Seville | Barriga A.,Institute Microelectronica Of Seville
BIOSIG 2013 - Proceedings of the 12th International Conference of the Biometrics Special Interest Group | Year: 2013

In this communication an embedded implementation of the Viola-Jones face detection algorithm targeting low frequency, low memory, and low power consumption, is presented. The design methodology, performance analysis and algorithm optimization in order to accelerate the face detection process, will be described. The resulted implementation is platform independent and achieves on average a 3 times detection speed up.

Ruiz-Amaya J.,Institute Microelectronica Of Seville | Rodriguez-Perez A.,Institute Microelectronica Of Seville | Delgado-Restituto M.,Institute Microelectronica Of Seville
Proceedings of the International Conference on Microelectronics, ICM | Year: 2010

This paper presents a comparative study of three low-noise amplifiers for neural recording applications. The topologies are thoroughly analysed in terms of area, power consumption and noise performance. Further, the theoretical results are confirmed by simulations of transistor-level implementations in a 0.13μm CMOS technology at 1.2V supply voltage. © 2009 IEEE.

Serrano-Gotarredona T.,Institute Microelectronica Of Seville | Linares-Barranco B.,Institute Microelectronica Of Seville
2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012 | Year: 2012

Memristive devices are a promising technology to implement dense learning synapse arrays emulating the high memory capacity and connectivity of biological brains. Recently, the implementation of STDP learning in memristive devices connected to spiking neurons have been demonstrated as well as the dependency of the form of the learning rule on the shape of the applied spike. In this paper, we propose a fully CMOS integrate-and-fire neuron generating a precisely shaped spike that can be tuned through programmable biases. The implementation of STDP learning is demonstrated through electrical simulations of a 4×4 array of memristors connected to 4 spiking neurons. © 2012 IEEE.

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