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Oliveira J.,Institute for the Development of New Technologies CTS UNINOVA | Oliveira J.,New University of Lisbon | Goes J.,New University of Lisbon | Figueiredo M.,Institute for the Development of New Technologies CTS UNINOVA | And 6 more authors.
IEEE Transactions on Circuits and Systems II: Express Briefs | Year: 2010

This brief presents an 8-bit 120-MS/s time-interleaved pipeline analog-to-digital converter (ADC) fully based on MOS discrete-time parametric amplification. The ADC, fabricated in a 130-nm CMOS logic process, features an active area below 0.12 mm2, where only MOS devices are used. Measurement results for a 20-MHz input signal shows that the ADC achieves 39.7 dB of signal-to-noise ratio, 49.3 dB of spurious-free dynamic range, -47.5 dB of total harmonic distortion, 39.1 dB of signal-to-noise-plus-distortion ratio, and 6.2 bits of peak effective number of bits while consuming less than 14 mW from a 1.2-V supply. © 2010 IEEE. Source

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